f35a407906
Update code from upstream repository https://github.com/lowRISC/opentitan to revision 5cae0cf1fac783e0d0df8c8597bf65322a696a56 * Allow different assertion "backends" in prim_assert.sv (Rupert Swarbrick) * [prim_prince/doc] Update documentation (Michael Schaffner) * [prim_prince] Add option to instantiate a registers half-way (Michael Schaffner) * [prim_cipher_pkg] Reuse sbox4_8bit to build wider sbox layers (Michael Schaffner) * [dv/prim] add PRESENT testbench (Udi Jonnalagadda) * [uvmdvgen] Scoreboard update. (Srikrishna Iyer) * [flash_ctrl dv] Fix V1 tests (Srikrishna Iyer) * [prim_cipher_pkg] Replicate common subfunctions for other widths (Michael Schaffner) * [prim/present] fix PRESENT decryption bugs (Udi Jonnalagadda) * [prim/present] fix some PRESENT encryption bugs (Udi Jonnalagadda) * [dv] Add get_mem DPI function to Verilator simutil (Stefan Wallentowitz) * [lint/entropy_src] Add the entropy source to the lint regression (Michael Schaffner) * [style-lint] Fix some common style lint warnings (Michael Schaffner) * first set of security checks added to D2 checklist (Scott Johnson) * [fpv/tooling] add FPV class extension in dvsim (Cindy Chen) * [dvsim/lint] Minor fixes for printout issues and result parser status (Michael Schaffner) * [syn] Print detailed messages to .md if publication is disabled (Michael Schaffner) * [prim_util] Do not use $clog2() in Xcelium (Philipp Wagner) * [prim] Update ResetValue parameter in prim_flop_2sync (Timothy Chen) * Modified some command-line arguments for DSim (Aimee Sutton) * [prim_util] Make prim_util a package (Philipp Wagner) * [dv] Move mem checking to scb (Weicai Yang) * [lint] Make PINCONNECTEMPTY Verilator waiver common (Philipp Wagner) * [prim] - Fix generic flash enum reference (Timothy Chen) * [prim_ram_*adv] Mark cfg port as unused (Philipp Wagner) * [prim_fifo_sync] Use vbits() for simpler code (Philipp Wagner) * [prim_flash] Add reset to held_part (Eunchan Kim) * [lint] Add more lint waivers (Philipp Wagner) * [dv] Add random backdoor for csr_hw_reset (Weicai Yang) * [dv] Add set_freq_khz in clk_rst_if (Weicai Yang) * [prim] Close GAPI file handle in primgen (Philipp Wagner) * [fpv/prim_packer] fix CI failure due to index out of bound (Cindy Chen) * [prim_arbiter_*] Propagate parameter changes (Michael Schaffner) * [prim_arbiter_tree] Fix incorrect arbitration behavior (Michael Schaffner) * [prim_arbiter_ppc] Add more FPV fairness checks (Michael Schaffner) * [prim_ram*] Add an assertion that checks wmask consistency (Michael Schaffner) * [memutil] Increase max memory width to 256bit (Tom Roberts) * [flash] - Add flash info page support (Timothy Chen) Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org> |
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| .. | ||
| dv_base_agent.sv | ||
| dv_base_agent_cfg.sv | ||
| dv_base_agent_cov.sv | ||
| dv_base_driver.sv | ||
| dv_base_env.sv | ||
| dv_base_env_cfg.sv | ||
| dv_base_env_cov.sv | ||
| dv_base_monitor.sv | ||
| dv_base_scoreboard.sv | ||
| dv_base_seq.sv | ||
| dv_base_sequencer.sv | ||
| dv_base_test.sv | ||
| dv_base_virtual_sequencer.sv | ||
| dv_base_vseq.sv | ||
| dv_lib.core | ||
| dv_lib_pkg.sv | ||
| README.md | ||
| title |
|---|
| DV Library Classes |
DV library classes
Overview
The DV library classes form the base layer / framework for constructing UVM testbenches. These classes provide features (settings, methods, hooks and other constructs used in verification) that are generic enough to be reused across all testbenches.
In this doc, we will capture some of the most salient / frequently used features in extended classes. These classes are being updated frequently. So, for a more detailed understanding, please read the class definitions directly.
The DV library classes fall into 3 categories - UVM RAL (register abstraction layer), UVM agent, and UVM environment extensions.
UVM RAL extensions
The RAL model generated using the [reggen]({{< relref "util/reggen/README.md" >}}) tool extend from these classes. These themselves extend from the corresponding RAL classes provided in UVM.
dv_base_reg_field
Currently, this class does not provide any additional features. One of the features planned for future is setting exclusion tags at the field level for the CSR suite of tests that will be extracted automatically from the Hjson-based IP CSR specification.
dv_base_reg
This class provides the following functions to support verification:
gen_n_used_bits(): This function returns the actual number of bits used in the CSR (sum of all available field widths).get_msb_pos(): This function returns the MSB bit position of all available fields. CSR either ends at this bit (bit `TL_DW - 1) or has reserved / invalid bits beyond this bit.
dv_base_reg_block
build(uvm_reg_addr_t base_addr): This function is implemented as a pseudo pure virtual function (returns a fatal error if called directly). It is used for building the complete RAL model. For a polymorphic approach, the DV user can use this class handle to create the extended (IP specific) class instance and call this function to build the actual RAL model. This is exactly how it is done in dv_base_env_cfg.
dv_base_reg_map
Currently, this class does not provide any additional features. Having this extension provides an opportunity to add common features in future.
UVM Agent extensions
TODO
UVM Environment extensions
TODO