ibex/vendor/lowrisc_ip/uvmdvgen/uvmdvgen.py
Rupert Swarbrick 1bbcce07ca Update opentitan vendor imports to lowRISC/opentitan@249b4c31
This commit was generated by running

    for hj in $(grep -l opentitan vendor/*.vendor.hjson); do
      $opentitan/util/vendor.py -U -c $hj
    done

and then squashing together all the resulting commits. It will be
followed by a patch that combines these vendor.hjson files (using the
vendor tool's new "mapping" functionality), but we need a patch first
to get everything in sync before squashing together.

Individual commit messages below:

*****

Update common_ifs to lowRISC/opentitan@249b4c31

Update code from subdir hw/dv/sv/common_ifs in upstream repository
https://github.com/lowRISC/opentitan to revision
249b4c316cd6626d13e17edd8a52ca60c004af96

* [dv] This fixes a padctrl reset issue in the chip level tb (Michael
  Schaffner)

*****

Update csr_utils to lowRISC/opentitan@249b4c31

Update code from subdir hw/dv/sv/csr_utils in upstream repository
https://github.com/lowRISC/opentitan to revision
249b4c316cd6626d13e17edd8a52ca60c004af96

* [dv] csr_excl_item printed msg cleanup (Srikrishna Iyer)
* [dv] Fix top-level mem test (Weicai Yang)
* [doc] Fix typo in CSR exclusions (Michael Schaffner)
* [dv] Fix failures in test csr_mem_rw_with_rand_reset (Weicai Yang)

*****

Update dv_lib to lowRISC/opentitan@249b4c31

Update code from subdir hw/dv/sv/dv_lib in upstream repository
https://github.com/lowRISC/opentitan to revision
249b4c316cd6626d13e17edd8a52ca60c004af96

* [dv/chip] fix csr_hw_reset X assertion issue (Cindy Chen)
* [dv] Use phase_ready_to_end to handle end of test (Weicai Yang)
* [dv] Fix failures in test csr_mem_rw_with_rand_reset (Weicai Yang)

*****

Update dv_utils to lowRISC/opentitan@249b4c31

Update code from subdir hw/dv/sv/dv_utils in upstream repository
https://github.com/lowRISC/opentitan to revision
249b4c316cd6626d13e17edd8a52ca60c004af96

* [dv] Use uvm_config_db to control tlul_assert (Weicai Yang)
* [dv] Add begin...end around if statement in macro (Weicai Yang)
* [dv] Fix timeout due to too many non-blocking TL accesses (Weicai
  Yang)
* [spi_device/dv] Add interrupt seq (Weicai Yang)

*****

Update dvsim to lowRISC/opentitan@249b4c31

Update code from subdir util/dvsim in upstream repository
https://github.com/lowRISC/opentitan to revision
249b4c316cd6626d13e17edd8a52ca60c004af96

* [dvsim] Enable round-trip of env variables into log (Philipp Wagner)
* [dvsim] Support for running pre-built SW tests (Srikrishna Iyer)
* [dvsim] Print what cmd is executed in the log (Srikrishna Iyer)
* [dvsim] Specify encoding of opened files as UTF-8 (Philipp Wagner)
* [dvsim] Simplify factory methods for FlowCfg (Rupert Swarbrick)
* [dvsim] small fix on css style (Cindy Chen)
* [dvsim] support css format for email (Cindy Chen)
* [doc] Rename Hardware -> Development Stages (Sam Elliott)

*****

Update uvmdvgen to lowRISC/opentitan@249b4c31

Update code from subdir util/uvmdvgen in upstream repository
https://github.com/lowRISC/opentitan to revision
249b4c316cd6626d13e17edd8a52ca60c004af96

* [uvmdvgen] Minor env gen fix (Srikrishna Iyer)
* [doc] Rename Hardware -> Development Stages (Sam Elliott)
* [dv] Use uvm_config_db to control tlul_assert (Weicai Yang)
* [uvmdvgen] Automate checklist gen, fixes (Srikrishna Iyer)
* [doc] Unify dashboard, manual spec table (Srikrishna Iyer)
* [dvsim] Added fusesoc generator for RAL (Srikrishna Iyer)
2020-05-26 16:41:48 +01:00

148 lines
5.1 KiB
Python
Executable file

#!/usr/bin/env python3
# Copyright lowRISC contributors.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
r"""Command-line tool to autogenerate boilerplate DV testbench code extended from dv_lib / cip_lib
"""
import argparse
import os
import sys
import gen_agent
import gen_env
def main():
parser = argparse.ArgumentParser(
description=__doc__,
formatter_class=argparse.RawDescriptionHelpFormatter)
parser.add_argument(
"name",
metavar="[ip/block name]",
help="Name of the ip/block for which the UVM TB is being auto-generated"
)
parser.add_argument(
"-a",
"--gen_agent",
action='store_true',
help="Generate UVM agent code extended from DV library")
parser.add_argument(
"-s",
"--has_separate_host_device_driver",
action='store_true',
help=
"""IP / block agent creates a separate driver for host and device modes.
(ignored if -a switch is not passed)""")
parser.add_argument("-e",
"--gen_env",
action='store_true',
help="Generate testbench UVM env code")
parser.add_argument(
"-c",
"--is_cip",
action='store_true',
help=
"""Is comportable IP - this will result in code being extended from CIP
library. If switch is not passed, then the code will be extended from
DV library instead. (ignored if -e switch is not passed)"""
)
parser.add_argument(
"-hr",
"--has_ral",
default=False,
action='store_true',
help="""Specify whether the DUT has CSRs and thus needs a UVM RAL model.
This option is required if either --is_cip or --has_interrupts are
enabled.""")
parser.add_argument(
"-hi",
"--has_interrupts",
default=False,
action='store_true',
help="""CIP has interrupts. Create interrupts interface in tb""")
parser.add_argument(
"-ha",
"--has_alerts",
default=False,
action='store_true',
help="""CIP has alerts. Create alerts interface in tb""")
parser.add_argument(
"-ea",
"--env_agents",
nargs="+",
metavar="agt1 agt2",
help="""Env creates an interface agent specified here. They are
assumed to already exist. Note that the list is space-separated,
and not comma-separated. (ignored if -e switch is not passed)"""
)
parser.add_argument(
"-ao",
"--agent_outdir",
metavar="[hw/dv/sv]",
help="""Path to place the agent code. A directory called <name>_agent is
created at this location. (default set to './<name>')"""
)
parser.add_argument(
"-eo",
"--env_outdir",
metavar="[hw/ip/<ip>]",
help=
"""Path to place the full tetsbench code. It creates 3 directories - dv, data and doc.
The DV plan and the testplan Hjson files are placed in the doc and data directories
respectively. These are to be merged into the IP's root directory (with the existing
data and doc directories). Under dv, it creates 3 sub-directories - env,
tb and tests to place all of the testbench sources. (default set to './<name>')"""
)
parser.add_argument(
"-m",
"--add-makefile",
default=False,
action='store_true',
help=
"""Tests are now run with dvsim.py tool that requires a hjson based sim cfg.
Setting this option will also result in the Makefile to be auto-generated (which is
the older way of building and running sims going through deprecation)."""
)
args = parser.parse_args()
if not args.agent_outdir: args.agent_outdir = args.name
if not args.env_outdir: args.env_outdir = args.name
# The has_ral option must be set if either is_cip or has_interrupts is set,
# as both require use of a RAL model. As such, it is disallowed to not have
# has_ral set if one of these options is set.
if not args.has_ral and (args.is_cip or args.has_interrupts):
args.has_ral = True
print("NOTE: --has_ral switch is enabled since either "
"--is_cip or --has_interrupts is set.")
if args.gen_agent:
gen_agent.gen_agent(args.name, \
args.has_separate_host_device_driver, \
args.agent_outdir)
if args.gen_env:
if not args.env_agents: args.env_agents = []
gen_env.gen_env(args.name, \
args.is_cip, \
args.has_ral, \
args.has_interrupts, \
args.has_alerts, \
args.env_agents, \
args.env_outdir, \
args.add_makefile)
if __name__ == '__main__':
main()