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4431023516
Add parameter `DbgHwBreakNum` to configure the number of HW breakpoints. The parameters controls the number of trigger registers available if debug support is enabled with `DbgTriggerEn`. Closes #1070
51 lines
2.7 KiB
ReStructuredText
51 lines
2.7 KiB
ReStructuredText
.. _debug-support:
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Debug Support
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=============
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Ibex offers support for execution-based debug according to the `RISC-V Debug Specification <https://riscv.org/specifications/debug-specification/>`_, version 0.13.
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.. note::
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Debug support in Ibex is only one of the components needed to build a System on Chip design with run-control debug support (think "the ability to attach GDB to a core over JTAG").
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Additionally, a Debug Module and a Debug Transport Module, compliant with the RISC-V Debug Specification, are needed.
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A supported open source implementation of these building blocks can be found in the `RISC-V Debug Support for PULP Cores IP block <https://github.com/pulp-platform/riscv-dbg/>`_.
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The `OpenTitan project <https://github.com/lowRISC/opentitan>`_ can serve as an example of how to integrate the two components in a toplevel design.
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Interface
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---------
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+-----------------+-----------+-----------------------------+
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| Signal | Direction | Description |
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+=================+===========+=============================+
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| ``debug_req_i`` | input | Request to enter Debug Mode |
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+-----------------+-----------+-----------------------------+
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``debug_req_i`` is the "debug interrupt", issued by the debug module when the core should enter Debug Mode.
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Parameters
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----------
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+---------------------+-----------------------------------------------------------------+
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| Parameter | Description |
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+=====================+=================================================================+
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| ``DmHaltAddr`` | Address to jump to when entering Debug Mode |
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+---------------------+-----------------------------------------------------------------+
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| ``DmExceptionAddr`` | Address to jump to when an exception occurs while in Debug Mode |
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+---------------------+-----------------------------------------------------------------+
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| ``DbgTriggerEn`` | Enable support for debug triggers |
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+---------------------+-----------------------------------------------------------------+
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| ``DbgHwBreakNum`` | Number of debug triggers |
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+---------------------+-----------------------------------------------------------------+
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Core Debug Registers
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--------------------
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Ibex implements four core debug registers, namely :ref:`csr-dcsr`, :ref:`csr-dpc`, and two debug scratch registers.
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If the ``DbgTriggerEn`` parameter is set, debug trigger registers are available.
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See :ref:`csr-tselect`, :ref:`csr-tdata1` and :ref:`csr-tdata2` for details.
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All those registers are accessible from Debug Mode only.
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If software tries to access them without the core being in Debug Mode, an illegal instruction exception is triggered.
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