mirror of
https://github.com/lowRISC/ibex.git
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28935490c2
This commit protects the core_busy_o signal using a multi-bit encoding to reduce the chances of an adversary for glitching this signal to low, thereby putting the core to sleep and e.g. not handling an alert. Without this commit, the glitch would only be detected once both the main core and the shadow core wake up again and the comparison of the core_busy_o signals continues. This resolves lowRISC/Ibex#1827. Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
458 lines
19 KiB
Systemverilog
458 lines
19 KiB
Systemverilog
// Copyright lowRISC contributors.
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// Licensed under the Apache License, Version 2.0, see LICENSE for details.
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// SPDX-License-Identifier: Apache-2.0
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// Ibex lockstep module
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// This module instantiates a second copy of the core logic, and compares it's outputs against
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// those from the main core. The second core runs synchronously with the main core, delayed by
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// LockstepOffset cycles.
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// SEC_CM: LOGIC.SHADOW
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module ibex_lockstep import ibex_pkg::*; #(
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parameter int unsigned LockstepOffset = 2,
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parameter bit PMPEnable = 1'b0,
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parameter int unsigned PMPGranularity = 0,
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parameter int unsigned PMPNumRegions = 4,
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parameter int unsigned MHPMCounterNum = 0,
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parameter int unsigned MHPMCounterWidth = 40,
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parameter bit RV32E = 1'b0,
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parameter rv32m_e RV32M = RV32MFast,
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parameter rv32b_e RV32B = RV32BNone,
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parameter bit BranchTargetALU = 1'b0,
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parameter bit WritebackStage = 1'b0,
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parameter bit ICache = 1'b0,
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parameter bit ICacheECC = 1'b0,
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parameter int unsigned BusSizeECC = BUS_SIZE,
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parameter int unsigned TagSizeECC = IC_TAG_SIZE,
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parameter int unsigned LineSizeECC = IC_LINE_SIZE,
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parameter bit BranchPredictor = 1'b0,
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parameter bit DbgTriggerEn = 1'b0,
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parameter int unsigned DbgHwBreakNum = 1,
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parameter bit ResetAll = 1'b0,
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parameter lfsr_seed_t RndCnstLfsrSeed = RndCnstLfsrSeedDefault,
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parameter lfsr_perm_t RndCnstLfsrPerm = RndCnstLfsrPermDefault,
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parameter bit SecureIbex = 1'b0,
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parameter bit DummyInstructions = 1'b0,
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parameter bit RegFileECC = 1'b0,
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parameter int unsigned RegFileDataWidth = 32,
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parameter bit MemECC = 1'b0,
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parameter int unsigned MemDataWidth = MemECC ? 32 + 7 : 32,
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parameter int unsigned DmHaltAddr = 32'h1A110800,
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parameter int unsigned DmExceptionAddr = 32'h1A110808
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) (
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input logic clk_i,
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input logic rst_ni,
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input logic [31:0] hart_id_i,
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input logic [31:0] boot_addr_i,
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input logic instr_req_i,
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input logic instr_gnt_i,
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input logic instr_rvalid_i,
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input logic [31:0] instr_addr_i,
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input logic [MemDataWidth-1:0] instr_rdata_i,
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input logic instr_err_i,
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input logic data_req_i,
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input logic data_gnt_i,
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input logic data_rvalid_i,
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input logic data_we_i,
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input logic [3:0] data_be_i,
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input logic [31:0] data_addr_i,
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input logic [MemDataWidth-1:0] data_wdata_i,
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input logic [MemDataWidth-1:0] data_rdata_i,
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input logic data_err_i,
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input logic dummy_instr_id_i,
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input logic [4:0] rf_raddr_a_i,
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input logic [4:0] rf_raddr_b_i,
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input logic [4:0] rf_waddr_wb_i,
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input logic rf_we_wb_i,
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input logic [RegFileDataWidth-1:0] rf_wdata_wb_ecc_i,
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input logic [RegFileDataWidth-1:0] rf_rdata_a_ecc_i,
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input logic [RegFileDataWidth-1:0] rf_rdata_b_ecc_i,
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input logic [IC_NUM_WAYS-1:0] ic_tag_req_i,
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input logic ic_tag_write_i,
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input logic [IC_INDEX_W-1:0] ic_tag_addr_i,
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input logic [TagSizeECC-1:0] ic_tag_wdata_i,
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input logic [TagSizeECC-1:0] ic_tag_rdata_i [IC_NUM_WAYS],
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input logic [IC_NUM_WAYS-1:0] ic_data_req_i,
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input logic ic_data_write_i,
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input logic [IC_INDEX_W-1:0] ic_data_addr_i,
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input logic [LineSizeECC-1:0] ic_data_wdata_i,
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input logic [LineSizeECC-1:0] ic_data_rdata_i [IC_NUM_WAYS],
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input logic ic_scr_key_valid_i,
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input logic ic_scr_key_req_i,
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input logic irq_software_i,
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input logic irq_timer_i,
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input logic irq_external_i,
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input logic [14:0] irq_fast_i,
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input logic irq_nm_i,
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input logic irq_pending_i,
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input logic debug_req_i,
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input crash_dump_t crash_dump_i,
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input logic double_fault_seen_i,
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input ibex_mubi_t fetch_enable_i,
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output logic alert_minor_o,
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output logic alert_major_internal_o,
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output logic alert_major_bus_o,
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input ibex_mubi_t core_busy_i,
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input logic test_en_i,
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input logic scan_rst_ni
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);
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localparam int unsigned LockstepOffsetW = $clog2(LockstepOffset);
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// Core outputs are delayed for an extra cycle due to shadow output registers
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localparam int unsigned OutputsOffset = LockstepOffset + 1;
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//////////////////////
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// Reset generation //
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//////////////////////
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// Upon reset, the comparison is stopped and the shadow core is reset, both immediately. A
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// counter is started. After LockstepOffset clock cycles:
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// - The counter is stopped.
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// - The reset of the shadow core is synchronously released.
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// The comparison is started in the following clock cycle.
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logic [LockstepOffsetW-1:0] rst_shadow_cnt_d, rst_shadow_cnt_q, rst_shadow_cnt_incr;
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// Internally generated resets cause IMPERFECTSCH warnings
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/* verilator lint_off IMPERFECTSCH */
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logic rst_shadow_set_d, rst_shadow_set_q;
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logic rst_shadow_n, enable_cmp_q;
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/* verilator lint_on IMPERFECTSCH */
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assign rst_shadow_cnt_incr = rst_shadow_cnt_q + 1'b1;
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assign rst_shadow_set_d = (rst_shadow_cnt_q == LockstepOffsetW'(LockstepOffset - 1));
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assign rst_shadow_cnt_d = rst_shadow_set_d ? rst_shadow_cnt_q : rst_shadow_cnt_incr;
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always_ff @(posedge clk_i or negedge rst_ni) begin
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if (!rst_ni) begin
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rst_shadow_cnt_q <= '0;
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enable_cmp_q <= '0;
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end else begin
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rst_shadow_cnt_q <= rst_shadow_cnt_d;
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enable_cmp_q <= rst_shadow_set_q;
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end
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end
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// The primitives below are used to place size-only constraints in order to prevent
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// synthesis optimizations and preserve anchor points for constraining backend tools.
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prim_flop #(
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.Width(1),
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.ResetValue(1'b0)
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) u_prim_rst_shadow_set_flop (
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.clk_i (clk_i),
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.rst_ni(rst_ni),
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.d_i (rst_shadow_set_d),
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.q_o (rst_shadow_set_q)
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);
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prim_clock_mux2 #(
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.NoFpgaBufG(1'b1)
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) u_prim_rst_shadow_n_mux2 (
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.clk0_i(rst_shadow_set_q),
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.clk1_i(scan_rst_ni),
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.sel_i (test_en_i),
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.clk_o (rst_shadow_n)
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);
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//////////////////
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// Input delays //
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//////////////////
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typedef struct packed {
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logic instr_gnt;
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logic instr_rvalid;
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logic [MemDataWidth-1:0] instr_rdata;
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logic instr_err;
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logic data_gnt;
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logic data_rvalid;
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logic [MemDataWidth-1:0] data_rdata;
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logic data_err;
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logic [RegFileDataWidth-1:0] rf_rdata_a_ecc;
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logic [RegFileDataWidth-1:0] rf_rdata_b_ecc;
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logic irq_software;
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logic irq_timer;
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logic irq_external;
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logic [14:0] irq_fast;
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logic irq_nm;
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logic debug_req;
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ibex_mubi_t fetch_enable;
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logic ic_scr_key_valid;
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} delayed_inputs_t;
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delayed_inputs_t [LockstepOffset-1:0] shadow_inputs_q;
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delayed_inputs_t shadow_inputs_in;
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// Packed arrays must be dealt with separately
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logic [TagSizeECC-1:0] shadow_tag_rdata_q [IC_NUM_WAYS][LockstepOffset];
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logic [LineSizeECC-1:0] shadow_data_rdata_q [IC_NUM_WAYS][LockstepOffset];
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// Assign the inputs to the delay structure
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assign shadow_inputs_in.instr_gnt = instr_gnt_i;
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assign shadow_inputs_in.instr_rvalid = instr_rvalid_i;
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assign shadow_inputs_in.instr_rdata = instr_rdata_i;
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assign shadow_inputs_in.instr_err = instr_err_i;
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assign shadow_inputs_in.data_gnt = data_gnt_i;
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assign shadow_inputs_in.data_rvalid = data_rvalid_i;
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assign shadow_inputs_in.data_rdata = data_rdata_i;
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assign shadow_inputs_in.data_err = data_err_i;
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assign shadow_inputs_in.rf_rdata_a_ecc = rf_rdata_a_ecc_i;
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assign shadow_inputs_in.rf_rdata_b_ecc = rf_rdata_b_ecc_i;
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assign shadow_inputs_in.irq_software = irq_software_i;
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assign shadow_inputs_in.irq_timer = irq_timer_i;
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assign shadow_inputs_in.irq_external = irq_external_i;
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assign shadow_inputs_in.irq_fast = irq_fast_i;
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assign shadow_inputs_in.irq_nm = irq_nm_i;
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assign shadow_inputs_in.debug_req = debug_req_i;
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assign shadow_inputs_in.fetch_enable = fetch_enable_i;
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assign shadow_inputs_in.ic_scr_key_valid = ic_scr_key_valid_i;
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// Delay the inputs
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always_ff @(posedge clk_i or negedge rst_ni) begin
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if (!rst_ni) begin
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for (int unsigned i = 0; i < LockstepOffset; i++) begin
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shadow_inputs_q[i] <= delayed_inputs_t'('0);
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shadow_tag_rdata_q[i] <= '{default: 0};
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shadow_data_rdata_q[i] <= '{default: 0};
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end
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end else begin
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for (int unsigned i = 0; i < LockstepOffset - 1; i++) begin
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shadow_inputs_q[i] <= shadow_inputs_q[i+1];
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shadow_tag_rdata_q[i] <= shadow_tag_rdata_q[i+1];
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shadow_data_rdata_q[i] <= shadow_data_rdata_q[i+1];
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end
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shadow_inputs_q[LockstepOffset-1] <= shadow_inputs_in;
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shadow_tag_rdata_q[LockstepOffset-1] <= ic_tag_rdata_i;
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shadow_data_rdata_q[LockstepOffset-1] <= ic_data_rdata_i;
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end
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end
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///////////////////
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// Output delays //
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///////////////////
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typedef struct packed {
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logic instr_req;
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logic [31:0] instr_addr;
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logic data_req;
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logic data_we;
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logic [3:0] data_be;
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logic [31:0] data_addr;
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logic [MemDataWidth-1:0] data_wdata;
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logic dummy_instr_id;
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logic [4:0] rf_raddr_a;
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logic [4:0] rf_raddr_b;
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logic [4:0] rf_waddr_wb;
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logic rf_we_wb;
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logic [RegFileDataWidth-1:0] rf_wdata_wb_ecc;
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logic [IC_NUM_WAYS-1:0] ic_tag_req;
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logic ic_tag_write;
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logic [IC_INDEX_W-1:0] ic_tag_addr;
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logic [TagSizeECC-1:0] ic_tag_wdata;
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logic [IC_NUM_WAYS-1:0] ic_data_req;
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logic ic_data_write;
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logic [IC_INDEX_W-1:0] ic_data_addr;
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logic [LineSizeECC-1:0] ic_data_wdata;
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logic ic_scr_key_req;
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logic irq_pending;
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crash_dump_t crash_dump;
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logic double_fault_seen;
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ibex_mubi_t core_busy;
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} delayed_outputs_t;
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delayed_outputs_t [OutputsOffset-1:0] core_outputs_q;
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delayed_outputs_t core_outputs_in;
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delayed_outputs_t shadow_outputs_d, shadow_outputs_q;
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// Assign core outputs to the structure
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assign core_outputs_in.instr_req = instr_req_i;
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assign core_outputs_in.instr_addr = instr_addr_i;
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assign core_outputs_in.data_req = data_req_i;
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assign core_outputs_in.data_we = data_we_i;
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assign core_outputs_in.data_be = data_be_i;
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assign core_outputs_in.data_addr = data_addr_i;
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assign core_outputs_in.data_wdata = data_wdata_i;
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assign core_outputs_in.dummy_instr_id = dummy_instr_id_i;
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assign core_outputs_in.rf_raddr_a = rf_raddr_a_i;
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assign core_outputs_in.rf_raddr_b = rf_raddr_b_i;
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assign core_outputs_in.rf_waddr_wb = rf_waddr_wb_i;
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assign core_outputs_in.rf_we_wb = rf_we_wb_i;
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assign core_outputs_in.rf_wdata_wb_ecc = rf_wdata_wb_ecc_i;
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assign core_outputs_in.ic_tag_req = ic_tag_req_i;
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assign core_outputs_in.ic_tag_write = ic_tag_write_i;
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assign core_outputs_in.ic_tag_addr = ic_tag_addr_i;
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assign core_outputs_in.ic_tag_wdata = ic_tag_wdata_i;
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assign core_outputs_in.ic_data_req = ic_data_req_i;
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assign core_outputs_in.ic_data_write = ic_data_write_i;
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assign core_outputs_in.ic_data_addr = ic_data_addr_i;
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assign core_outputs_in.ic_data_wdata = ic_data_wdata_i;
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assign core_outputs_in.ic_scr_key_req = ic_scr_key_req_i;
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assign core_outputs_in.irq_pending = irq_pending_i;
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assign core_outputs_in.crash_dump = crash_dump_i;
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assign core_outputs_in.double_fault_seen = double_fault_seen_i;
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assign core_outputs_in.core_busy = core_busy_i;
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// Delay the outputs
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always_ff @(posedge clk_i) begin
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for (int unsigned i = 0; i < OutputsOffset - 1; i++) begin
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core_outputs_q[i] <= core_outputs_q[i+1];
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end
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core_outputs_q[OutputsOffset-1] <= core_outputs_in;
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end
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///////////////////////////////
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// Shadow core instantiation //
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///////////////////////////////
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logic shadow_alert_minor, shadow_alert_major_internal, shadow_alert_major_bus;
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ibex_core #(
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.PMPEnable ( PMPEnable ),
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.PMPGranularity ( PMPGranularity ),
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.PMPNumRegions ( PMPNumRegions ),
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.MHPMCounterNum ( MHPMCounterNum ),
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.MHPMCounterWidth ( MHPMCounterWidth ),
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.RV32E ( RV32E ),
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.RV32M ( RV32M ),
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.RV32B ( RV32B ),
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.BranchTargetALU ( BranchTargetALU ),
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.ICache ( ICache ),
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.ICacheECC ( ICacheECC ),
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.BusSizeECC ( BusSizeECC ),
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.TagSizeECC ( TagSizeECC ),
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.LineSizeECC ( LineSizeECC ),
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.BranchPredictor ( BranchPredictor ),
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.DbgTriggerEn ( DbgTriggerEn ),
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.DbgHwBreakNum ( DbgHwBreakNum ),
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.WritebackStage ( WritebackStage ),
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.ResetAll ( ResetAll ),
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.RndCnstLfsrSeed ( RndCnstLfsrSeed ),
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.RndCnstLfsrPerm ( RndCnstLfsrPerm ),
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.SecureIbex ( SecureIbex ),
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.DummyInstructions ( DummyInstructions ),
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.RegFileECC ( RegFileECC ),
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.RegFileDataWidth ( RegFileDataWidth ),
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.MemECC ( MemECC ),
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.MemDataWidth ( MemDataWidth ),
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.DmHaltAddr ( DmHaltAddr ),
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.DmExceptionAddr ( DmExceptionAddr )
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) u_shadow_core (
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.clk_i (clk_i),
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.rst_ni (rst_shadow_n),
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.hart_id_i (hart_id_i),
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.boot_addr_i (boot_addr_i),
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.instr_req_o (shadow_outputs_d.instr_req),
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.instr_gnt_i (shadow_inputs_q[0].instr_gnt),
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.instr_rvalid_i (shadow_inputs_q[0].instr_rvalid),
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.instr_addr_o (shadow_outputs_d.instr_addr),
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.instr_rdata_i (shadow_inputs_q[0].instr_rdata),
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.instr_err_i (shadow_inputs_q[0].instr_err),
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.data_req_o (shadow_outputs_d.data_req),
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.data_gnt_i (shadow_inputs_q[0].data_gnt),
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.data_rvalid_i (shadow_inputs_q[0].data_rvalid),
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.data_we_o (shadow_outputs_d.data_we),
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.data_be_o (shadow_outputs_d.data_be),
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.data_addr_o (shadow_outputs_d.data_addr),
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.data_wdata_o (shadow_outputs_d.data_wdata),
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.data_rdata_i (shadow_inputs_q[0].data_rdata),
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.data_err_i (shadow_inputs_q[0].data_err),
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.dummy_instr_id_o (shadow_outputs_d.dummy_instr_id),
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.rf_raddr_a_o (shadow_outputs_d.rf_raddr_a),
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.rf_raddr_b_o (shadow_outputs_d.rf_raddr_b),
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.rf_waddr_wb_o (shadow_outputs_d.rf_waddr_wb),
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.rf_we_wb_o (shadow_outputs_d.rf_we_wb),
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.rf_wdata_wb_ecc_o (shadow_outputs_d.rf_wdata_wb_ecc),
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.rf_rdata_a_ecc_i (shadow_inputs_q[0].rf_rdata_a_ecc),
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.rf_rdata_b_ecc_i (shadow_inputs_q[0].rf_rdata_b_ecc),
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.ic_tag_req_o (shadow_outputs_d.ic_tag_req),
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.ic_tag_write_o (shadow_outputs_d.ic_tag_write),
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.ic_tag_addr_o (shadow_outputs_d.ic_tag_addr),
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.ic_tag_wdata_o (shadow_outputs_d.ic_tag_wdata),
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.ic_tag_rdata_i (shadow_tag_rdata_q[0]),
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.ic_data_req_o (shadow_outputs_d.ic_data_req),
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.ic_data_write_o (shadow_outputs_d.ic_data_write),
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.ic_data_addr_o (shadow_outputs_d.ic_data_addr),
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.ic_data_wdata_o (shadow_outputs_d.ic_data_wdata),
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.ic_data_rdata_i (shadow_data_rdata_q[0]),
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.ic_scr_key_valid_i (shadow_inputs_q[0].ic_scr_key_valid),
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.ic_scr_key_req_o (shadow_outputs_d.ic_scr_key_req),
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|
|
|
.irq_software_i (shadow_inputs_q[0].irq_software),
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|
.irq_timer_i (shadow_inputs_q[0].irq_timer),
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.irq_external_i (shadow_inputs_q[0].irq_external),
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|
.irq_fast_i (shadow_inputs_q[0].irq_fast),
|
|
.irq_nm_i (shadow_inputs_q[0].irq_nm),
|
|
.irq_pending_o (shadow_outputs_d.irq_pending),
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|
|
|
.debug_req_i (shadow_inputs_q[0].debug_req),
|
|
.crash_dump_o (shadow_outputs_d.crash_dump),
|
|
.double_fault_seen_o (shadow_outputs_d.double_fault_seen),
|
|
|
|
`ifdef RVFI
|
|
.rvfi_valid (),
|
|
.rvfi_order (),
|
|
.rvfi_insn (),
|
|
.rvfi_trap (),
|
|
.rvfi_halt (),
|
|
.rvfi_intr (),
|
|
.rvfi_mode (),
|
|
.rvfi_ixl (),
|
|
.rvfi_rs1_addr (),
|
|
.rvfi_rs2_addr (),
|
|
.rvfi_rs3_addr (),
|
|
.rvfi_rs1_rdata (),
|
|
.rvfi_rs2_rdata (),
|
|
.rvfi_rs3_rdata (),
|
|
.rvfi_rd_addr (),
|
|
.rvfi_rd_wdata (),
|
|
.rvfi_pc_rdata (),
|
|
.rvfi_pc_wdata (),
|
|
.rvfi_mem_addr (),
|
|
.rvfi_mem_rmask (),
|
|
.rvfi_mem_wmask (),
|
|
.rvfi_mem_rdata (),
|
|
.rvfi_mem_wdata (),
|
|
.rvfi_ext_mip (),
|
|
.rvfi_ext_nmi (),
|
|
.rvfi_ext_debug_req (),
|
|
.rvfi_ext_mcycle (),
|
|
.rvfi_ext_mhpmcounters (),
|
|
.rvfi_ext_mhpmcountersh (),
|
|
.rvfi_ext_ic_scr_key_valid (),
|
|
`endif
|
|
|
|
.fetch_enable_i (shadow_inputs_q[0].fetch_enable),
|
|
.alert_minor_o (shadow_alert_minor),
|
|
.alert_major_internal_o (shadow_alert_major_internal),
|
|
.alert_major_bus_o (shadow_alert_major_bus),
|
|
.core_busy_o (shadow_outputs_d.core_busy)
|
|
);
|
|
|
|
// Register the shadow core outputs
|
|
always_ff @(posedge clk_i) begin
|
|
shadow_outputs_q <= shadow_outputs_d;
|
|
end
|
|
|
|
/////////////////////////
|
|
// Compare the outputs //
|
|
/////////////////////////
|
|
|
|
logic outputs_mismatch;
|
|
|
|
assign outputs_mismatch = enable_cmp_q & (shadow_outputs_q != core_outputs_q[0]);
|
|
assign alert_major_internal_o = outputs_mismatch | shadow_alert_major_internal;
|
|
assign alert_major_bus_o = shadow_alert_major_bus;
|
|
assign alert_minor_o = shadow_alert_minor;
|
|
|
|
endmodule
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