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115 lines
2.9 KiB
C
115 lines
2.9 KiB
C
// Copyright lowRISC contributors.
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// Licensed under the Apache License, Version 2.0, see LICENSE for details.
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// SPDX-License-Identifier: Apache-2.0
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#ifndef SIMPLE_SYSTEM_COMMON_H__
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#include <stdint.h>
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#include "simple_system_regs.h"
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#define DEV_WRITE(addr, val) (*((volatile uint32_t *)(addr)) = val)
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#define DEV_READ(addr, val) (*((volatile uint32_t *)(addr)))
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#define PCOUNT_READ(name, dst) asm volatile("csrr %0, " #name ";" : "=r"(dst))
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/**
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* Writes character to simulator out log. Signature matches c stdlib function
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* of the same name.
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*
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* @param c Character to output
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* @returns Character output (never fails so no EOF ever returned)
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*/
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int putchar(int c);
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/**
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* Writes string to simulator out log. Signature matches c stdlib function of
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* the same name.
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*
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* @param str String to output
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* @returns 0 always (never fails so no error)
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*/
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int puts(const char *str);
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/**
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* Writes ASCII hex representation of number to simulator out log.
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*
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* @param h Number to output in hex
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*/
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void puthex(uint32_t h);
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/**
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* Immediately halts the simulation
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*/
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void sim_halt();
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/**
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* Enables/disables performance counters. This effects mcycle and minstret as
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* well as the mhpmcounterN counters.
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*
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* @param enable if non-zero enables, otherwise disables
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*/
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static inline void pcount_enable(int enable) {
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// Note cycle is disabled with everything else
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unsigned int inhibit_val = enable ? 0x0 : 0xFFFFFFFF;
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// CSR 0x320 was called `mucounteren` in the privileged spec v1.9.1, it was
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// then dropped in v1.10, and then re-added in v1.11 with the name
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// `mcountinhibit`. Unfortunately, the version of binutils we use only allows
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// the old name, and LLVM only supports the new name (though this is changed
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// on trunk to support both), so we use the numeric value here for maximum
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// compatibility.
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asm volatile("csrw 0x320, %0\n" : : "r"(inhibit_val));
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}
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/**
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* Resets all performance counters. This effects mcycle and minstret as well
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* as the mhpmcounterN counters.
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*/
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void pcount_reset();
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/**
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* Enables timer interrupt
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*
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* @param time_base Number of time ticks to count before interrupt
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*/
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void timer_enable(uint64_t time_base);
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/**
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* Returns current mtime value
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*/
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uint64_t timer_read(void);
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/**
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* Set a new timer value
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*
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* @param new_time New value for time
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*/
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void timecmp_update(uint64_t new_time);
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/**
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* Disables timer interrupt
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*/
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void timer_disable(void);
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/**
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* Returns current global time value
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*/
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uint64_t get_elapsed_time(void);
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/**
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* Enables/disables the instruction cache. This has no effect on Ibex
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* configurations that do not have an instruction cache and in particular is
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* safe to execute on those configurations.
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*
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* @param enable if non-zero enables, otherwise disables
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*/
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static inline void icache_enable(int enable) {
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if (enable) {
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// Set icache enable bit in CPUCTRLSTS
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asm volatile("csrs 0x7c0, 1");
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} else {
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// Clear icache enable bit in CPUCTRLSTS
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asm volatile("csrc 0x7c0, 1");
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}
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}
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#endif
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