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When targeting Xilinx FPGAs, we utilize a DSP for counters with a width of less than 49-bit. In this case, a sync. reset is needed. However, currently, there is a bug in the RTL where also a sync. reset is used for the non-DSP counters on the FPGA. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org>
111 lines
3.4 KiB
Systemverilog
111 lines
3.4 KiB
Systemverilog
// Copyright lowRISC contributors.
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// Licensed under the Apache License, Version 2.0, see LICENSE for details.
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// SPDX-License-Identifier: Apache-2.0
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module ibex_counter #(
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parameter int CounterWidth = 32,
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// When set `counter_val_upd_o` provides an incremented version of the counter value, otherwise
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// the output is hard-wired to 0. This is required to allow Xilinx DSP inference to work
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// correctly. When `ProvideValUpd` is set no DSPs are inferred.
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parameter bit ProvideValUpd = 0
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) (
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input logic clk_i,
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input logic rst_ni,
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input logic counter_inc_i,
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input logic counterh_we_i,
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input logic counter_we_i,
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input logic [31:0] counter_val_i,
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output logic [63:0] counter_val_o,
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output logic [63:0] counter_val_upd_o
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);
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logic [63:0] counter;
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logic [CounterWidth-1:0] counter_upd;
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logic [63:0] counter_load;
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logic we;
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logic [CounterWidth-1:0] counter_d;
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// Increment
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assign counter_upd = counter[CounterWidth-1:0] + {{CounterWidth - 1{1'b0}}, 1'b1};
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// Update
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always_comb begin
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// Write
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we = counter_we_i | counterh_we_i;
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counter_load[63:32] = counter[63:32];
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counter_load[31:0] = counter_val_i;
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if (counterh_we_i) begin
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counter_load[63:32] = counter_val_i;
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counter_load[31:0] = counter[31:0];
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end
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// Next value logic
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if (we) begin
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counter_d = counter_load[CounterWidth-1:0];
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end else if (counter_inc_i) begin
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counter_d = counter_upd[CounterWidth-1:0];
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end else begin
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counter_d = counter[CounterWidth-1:0];
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end
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end
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`ifdef FPGA_XILINX
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// On Xilinx FPGAs, 48-bit DSPs are available that can be used for the
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// counter. Hence, use Xilinx specific flop implementation. The datatype for
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// UseDsp is on purpose int as with string Xilinx throws an error for the
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// use_dsp pragma.
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localparam int UseDsp = CounterWidth < 49 ? "yes" : "no";
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(* use_dsp = UseDsp *) logic [CounterWidth-1:0] counter_q;
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`else
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localparam int UseDsp = "no";
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logic [CounterWidth-1:0] counter_q;
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`endif
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if (UseDsp == "yes") begin : g_cnt_dsp
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// Use sync. reset for DSP.
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always_ff @(posedge clk_i) begin
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if (!rst_ni) begin
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counter_q <= '0;
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end else begin
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counter_q <= counter_d;
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end
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end
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end else begin : g_cnt_no_dsp
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// Use async. reset for flop.
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always_ff @(posedge clk_i or negedge rst_ni) begin
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if (!rst_ni) begin
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counter_q <= '0;
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end else begin
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counter_q <= counter_d;
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end
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end
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end
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if (CounterWidth < 64) begin : g_counter_narrow
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logic [63:CounterWidth] unused_counter_load;
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assign counter[CounterWidth-1:0] = counter_q;
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assign counter[63:CounterWidth] = '0;
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if (ProvideValUpd) begin : g_counter_val_upd_o
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assign counter_val_upd_o[CounterWidth-1:0] = counter_upd;
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end else begin : g_no_counter_val_upd_o
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assign counter_val_upd_o[CounterWidth-1:0] = '0;
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end
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assign counter_val_upd_o[63:CounterWidth] = '0;
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assign unused_counter_load = counter_load[63:CounterWidth];
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end else begin : g_counter_full
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assign counter = counter_q;
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if (ProvideValUpd) begin : g_counter_val_upd_o
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assign counter_val_upd_o = counter_upd;
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end else begin : g_no_counter_val_upd_o
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assign counter_val_upd_o = '0;
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end
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end
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assign counter_val_o = counter;
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endmodule
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