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35abca14ab
- Add a technology map for latches (only works with nandgate45 library at the moment) - Add a real latch-based clock gating cell - Update timing path reporting to differentiate between register and latch paths - Update summary results in README to reflect the latch-based numbers, plus add numbers for a micro-riscy-style (RV32EC) config Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
23 lines
452 B
Verilog
23 lines
452 B
Verilog
// Copyright lowRISC contributors.
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// Licensed under the Apache License, Version 2.0, see LICENSE for details.
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// SPDX-License-Identifier: Apache-2.0
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// Example clock gating module for yosys synthesis
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module prim_clock_gating (
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input clk_i,
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input en_i,
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input test_en_i,
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output clk_o
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);
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reg en_latch;
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always @* begin
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if (!clk_i) begin
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en_latch = en_i | test_en_i;
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end
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end
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assign clk_o = en_latch & clk_i;
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endmodule
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