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45 lines
1.4 KiB
Text
45 lines
1.4 KiB
Text
CAPI=2:
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# Copyright lowRISC contributors.
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# Licensed under the Apache License, Version 2.0, see LICENSE for details.
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# SPDX-License-Identifier: Apache-2.0
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name: "lowrisc:util:sv2v:0.1"
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description: "Script to convert SystemVerilog files to Verilog with sv2v"
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filesets:
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files_sv2v_in_place:
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files:
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- sv2v_in_place.py : { copyto: util/sv2v_in_place.py }
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scripts:
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sv2v_in_place:
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cmd:
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- python3
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- util/sv2v_in_place.py
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- --incdir-list=incdirs.txt
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# A bit of a hack: The primitives directory (vendored from OpenTitan)
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# contains SystemVerilog code that has proper SVA assertions, using
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# things like the |-> operator.
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#
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# The Yosys-style prim_assert.sv assertions are immediate, rather than
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# concurrent. Such assertions only allow expressions (not full property
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# specifiers), which cause a syntax error if you try to use them with
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# the assertions in the primitives directory.
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#
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# Since we don't care about those assertions here, we want to strip
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# them out. The code that selects an assertion backend in
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# prim_assert.sv doesn't have an explicit "NO_ASSERTIONS" mode, but
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# "SYNTHESIS" implies the same thing, so we use that.
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- --define-if=prim:SYNTHESIS
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- -DYOSYS
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- -DFORMAL
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- -v
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- files.txt
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targets:
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default:
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filesets:
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- files_sv2v_in_place
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hooks:
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pre_build:
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- sv2v_in_place
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