mirror of
https://github.com/lowRISC/ibex.git
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Updated the parameters with respect to top_earlgrey.hjson in OpenTitan repository. For other builds, kept the previously undeclared parameters as their default values. Signed-off-by: Canberk Topal <ctopal@lowrisc.org>
204 lines
5.1 KiB
Text
204 lines
5.1 KiB
Text
CAPI=2:
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# Copyright lowRISC contributors.
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# Licensed under the Apache License, Version 2.0, see LICENSE for details.
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# SPDX-License-Identifier: Apache-2.0
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name: "lowrisc:ibex:ibex_core:0.1"
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description: "Ibex CPU Core Components"
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filesets:
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files_rtl:
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depend:
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- lowrisc:prim:assert
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- lowrisc:prim:clock_gating
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- lowrisc:prim:lfsr
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- lowrisc:ibex:ibex_pkg
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- lowrisc:ibex:ibex_icache
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- lowrisc:dv:dv_fcov_macros
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files:
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- rtl/ibex_alu.sv
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- rtl/ibex_branch_predict.sv
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- rtl/ibex_compressed_decoder.sv
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- rtl/ibex_controller.sv
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- rtl/ibex_cs_registers.sv
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- rtl/ibex_csr.sv
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- rtl/ibex_counter.sv
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- rtl/ibex_decoder.sv
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- rtl/ibex_ex_block.sv
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- rtl/ibex_fetch_fifo.sv
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- rtl/ibex_id_stage.sv
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- rtl/ibex_if_stage.sv
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- rtl/ibex_load_store_unit.sv
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- rtl/ibex_multdiv_fast.sv
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- rtl/ibex_multdiv_slow.sv
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- rtl/ibex_prefetch_buffer.sv
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- rtl/ibex_pmp.sv
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- rtl/ibex_wb_stage.sv
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- rtl/ibex_dummy_instr.sv
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- rtl/ibex_core.sv
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- rtl/ibex_pmp_reset_default.svh: {is_include_file: true}
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file_type: systemVerilogSource
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files_lint_verilator:
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files:
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- lint/verilator_waiver.vlt: {file_type: vlt}
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files_lint_verible:
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files:
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- lint/verible_waiver.vbw: {file_type: veribleLintWaiver}
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files_check_tool_requirements:
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depend:
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- lowrisc:tool:check_tool_requirements
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parameters:
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RVFI:
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datatype: bool
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paramtype: vlogdefine
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SYNTHESIS:
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datatype: bool
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paramtype: vlogdefine
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FPGA_XILINX:
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datatype: bool
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description: Identifies Xilinx FPGA targets to set DSP pragmas for performance counters.
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default: false
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paramtype: vlogdefine
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RV32E:
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datatype: int
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default: 0
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paramtype: vlogparam
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RV32M:
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datatype: str
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default: ibex_pkg::RV32MFast
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paramtype: vlogdefine
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description: "RV32M implementation parameter enum. See the ibex_pkg::rv32m_e enum in ibex_pkg.sv for permitted values."
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RV32B:
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datatype: str
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default: ibex_pkg::RV32BNone
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paramtype: vlogdefine
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description: "Bitmanip implementation parameter enum. See the ibex_pkg::rv32b_e enum in ibex_pkg.sv for permitted values."
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RegFile:
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datatype: str
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default: ibex_pkg::RegFileFF
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paramtype: vlogdefine
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description: "Register file implementation parameter enum. See the ibex_pkg::regfile_e enum in ibex_pkg.sv for permitted values."
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ICache:
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datatype: int
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default: 0
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paramtype: vlogparam
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description: "Enable instruction cache"
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ICacheECC:
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datatype: int
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default: 0
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paramtype: vlogparam
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description: "Enable ECC protection in instruction cache"
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BranchTargetALU:
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datatype: int
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default: 0
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paramtype: vlogparam
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description: "Enables separate branch target ALU (increasing branch performance EXPERIMENTAL) [0/1]"
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WritebackStage:
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datatype: int
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default: 0
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paramtype: vlogparam
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description: "Enables third pipeline stage (EXPERIMENTAL) [0/1]"
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BranchPredictor:
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datatype: int
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paramtype: vlogparam
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default: 0
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description: "Enables static branch prediction (EXPERIMENTAL)"
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DbgTriggerEn:
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datatype: int
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default: 0
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paramtype: vlogparam
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description: "Enable support for debug triggers. "
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SecureIbex:
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datatype: int
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default: 0
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paramtype: vlogparam
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description: "Enables security hardening features (EXPERIMENTAL) [0/1]"
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ICacheScramble:
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datatype: int
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default: 0
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paramtype: vlogparam
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description: "Enables ICache scrambling feature (EXPERIMENTAL) [0/1]"
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PMPEnable:
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datatype: int
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default: 0
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paramtype: vlogparam
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description: "Enable PMP"
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PMPGranularity:
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datatype: int
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default: 0
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paramtype: vlogparam
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description: "Granularity of NAPOT range, 0 = 4 byte, 1 = byte, 2 = 16 byte, 3 = 32 byte etc"
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PMPNumRegions:
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datatype: int
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default: 4
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paramtype: vlogparam
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description: "Number of PMP regions"
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MHPMCounterNum:
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datatype: int
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paramtype: vlogparam
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default: 0
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description: Number of performance monitor event counters [0/29]
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MHPMCounterWidth:
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datatype: int
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paramtype: vlogparam
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default: 40
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description: Bit width of performance monitor event counters [32/64]
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targets:
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default: &default_target
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filesets:
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- tool_verilator ? (files_lint_verilator)
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- tool_veriblelint ? (files_lint_verible)
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- files_rtl
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- files_check_tool_requirements
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toplevel: ibex_core
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parameters:
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- tool_vivado ? (FPGA_XILINX=true)
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lint:
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<<: *default_target
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parameters:
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- SYNTHESIS=true
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- RVFI=true
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default_tool: verilator
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tools:
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verilator:
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mode: lint-only
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verilator_options:
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- "-Wall"
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# RAM primitives wider than 64bit (required for ECC) fail to build in
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# Verilator without increasing the unroll count (see Verilator#1266)
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- "--unroll-count 72"
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format:
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filesets:
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- files_rtl
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parameters:
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- SYNTHESIS=true
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- RVFI=true
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default_tool: veribleformat
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toplevel: ibex_core
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tools:
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veribleformat:
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verible_format_args:
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- "--inplace"
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