mirror of
https://github.com/lowRISC/ibex.git
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dcdd982686
This doesn't produce a lint warning in the version of verilator currently used in CI but does produce a warning in newer versions.
72 lines
3.4 KiB
Text
72 lines
3.4 KiB
Text
// Copyright lowRISC contributors.
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// Licensed under the Apache License, Version 2.0, see LICENSE for details.
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// SPDX-License-Identifier: Apache-2.0
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// Lint waivers for Verilator
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// See https://www.veripool.org/projects/verilator/wiki/Manual-verilator#CONFIGURATION-FILES
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// for documentation.
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//
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// Important: This file must included *before* any other Verilog file is read.
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// Otherwise, only global waivers are applied, but not file-specific waivers.
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`verilator_config
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lint_off -rule PINCONNECTEMPTY
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// We have some boolean top-level parameters in e.g. ibex_core_tracing.sv.
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// When building with fusesoc, these get set with defines like
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// -GRV32M=1 (rather than -GRV32M=1'b1), leading to warnings like:
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//
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// Operator VAR '<varname>' expects 1 bits on the Initial value, but
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// Initial value's CONST '32'h1' generates 32 bits.
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//
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// This signoff rule ignores errors like this. Note that it only
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// matches when you set a 1-bit value to a literal 1, so it won't hide
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// silly mistakes like setting it to 2.
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//
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lint_off -rule WIDTH -file "*/rtl/ibex_top_tracing.sv"
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-match "*expects 1 bits*Initial value's CONST '32'h1'*"
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// Operator expects 1 bit on initial value but initial value's CONST generates
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// 32 bits, need a specific RV32B waiver as it uses enums so the above catch-all
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// waiver doesn't work.
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lint_off -rule WIDTH -file "*/rtl/ibex_top_tracing.sv" -match "*'RV32B'*"
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// Bits of signal are not used: be_i[3:1]
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// Bits of signal are not used: addr_i[31:10,1:0]
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// Bits of signal are not used: wdata_i[31:8]
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//
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// simulator_ctrl exposes a 32-bit write-only interface to its control
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// registers, but actually only looks at the bottom byte and rounds addresses
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// down to be 4-byte aligned.
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//
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lint_off -rule UNUSED -file "*/rtl/sim/simulator_ctrl.sv" -match "*'be_i'[3:1]*"
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lint_off -rule UNUSED -file "*/rtl/sim/simulator_ctrl.sv" -match "*'addr_i'[31:10,1:0]*"
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lint_off -rule UNUSED -file "*/rtl/sim/simulator_ctrl.sv" -match "*'wdata_i'[31:8]*"
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// Bits of signal are not used: timer_addr_i[31:10]
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//
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// The upper bits of this address are used to select whether the timer is
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// addressed at all (encoded in the timer_req_i input). However, we pass the
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// entire 32-bit address around to make the code a bit cleaner.
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lint_off -rule UNUSED -file "*/rtl/timer.sv" -match "*'timer_addr_i'[31:10]*"
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// Signal is not used: clk_i
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// leaving clk and reset connected in-case we want to add assertions
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lint_off -rule UNUSED -file "*/rtl/ibex_pmp.sv" -match "*clk_i*"
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lint_off -rule UNUSED -file "*/rtl/ibex_compressed_decoder.sv" -match "*clk_i*"
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lint_off -rule UNUSED -file "*/rtl/ibex_decoder.sv" -match "*clk_i*"
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lint_off -rule UNUSED -file "*/rtl/ibex_branch_predict.sv" -match "*clk_i*"
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// Signal is not used: rst_ni
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// leaving clk and reset connected in-case we want to add assertions
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lint_off -rule UNUSED -file "*/rtl/ibex_pmp.sv" -match "*rst_ni*"
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lint_off -rule UNUSED -file "*/rtl/ibex_compressed_decoder.sv" -match "*rst_ni*"
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lint_off -rule UNUSED -file "*/rtl/ibex_decoder.sv" -match "*rst_ni*"
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lint_off -rule UNUSED -file "*/rtl/ibex_branch_predict.sv" -match "*rst_ni*"
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// Temporary waivers until OpenTitan primitives are lint-clean
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// https://github.com/lowRISC/opentitan/issues/2313
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lint_off -file "*/lowrisc_prim_*/rtl/*.sv"
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lint_off -rule UNUSED -file "*/rtl/ibex_top_tracing.sv" -match "*RndCnstLfsrSeed*"
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lint_off -rule UNUSED -file "*/rtl/ibex_top_tracing.sv" -match "*RndCnstLfsrPerm*"
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