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ab3ec361be
step on a jal instruction (from Olivier Montfort) ra register not update when single step debug #3
536 lines
18 KiB
Systemverilog
536 lines
18 KiB
Systemverilog
// Copyright 2017 ETH Zurich and University of Bologna.
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// Copyright and related rights are licensed under the Solderpad Hardware
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// License, Version 0.51 (the “License”); you may not use this file except in
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// compliance with the License. You may obtain a copy of the License at
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// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
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// or agreed to in writing, software, hardware and materials distributed under
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// this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR
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// CONDITIONS OF ANY KIND, either express or implied. See the License for the
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// specific language governing permissions and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////
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// Engineer: Matthias Baer - baermatt@student.ethz.ch //
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// //
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// Additional contributions by: //
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// Igor Loi - igor.loi@unibo.it //
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// Andreas Traber - atraber@student.ethz.ch //
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// Sven Stucki - svstucki@student.ethz.ch //
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// Davide Schiavone - pschiavo@iis.ee.ethz.ch //
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// //
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// Design Name: Main controller //
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// Project Name: zero-riscy //
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// Language: SystemVerilog //
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// //
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// Description: Main CPU controller of the processor //
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// //
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////////////////////////////////////////////////////////////////////////////////
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`include "zeroriscy_config.sv"
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import zeroriscy_defines::*;
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module zeroriscy_controller
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#(
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parameter REG_ADDR_WIDTH = 5
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)
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(
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input logic clk,
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input logic rst_n,
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input logic fetch_enable_i, // Start the decoding
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output logic ctrl_busy_o, // Core is busy processing instructions
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output logic first_fetch_o, // Core is at the FIRST FETCH stage
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output logic is_decoding_o, // Core is in decoding state
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// decoder related signals
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output logic deassert_we_o, // deassert write enable for next instruction
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input logic illegal_insn_i, // decoder encountered an invalid instruction
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input logic ecall_insn_i, // ecall encountered an mret instruction
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input logic mret_insn_i, // decoder encountered an mret instruction
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input logic pipe_flush_i, // decoder wants to do a pipe flush
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input logic ebrk_insn_i, // decoder encountered an ebreak instruction
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input logic csr_status_i, // decoder encountered an csr status instruction
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// from IF/ID pipeline
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input logic instr_valid_i, // instruction coming from IF/ID pipeline is valid
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// from prefetcher
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output logic instr_req_o, // Start fetching instructions
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// to prefetcher
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output logic pc_set_o, // jump to address set by pc_mux
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output logic [2:0] pc_mux_o, // Selector in the Fetch stage to select the rigth PC (normal, jump ...)
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output logic [1:0] exc_pc_mux_o, // Selects target PC for exception
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// LSU
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input logic data_misaligned_i,
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// jump/branch signals
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input logic branch_in_id_i, // branch in id
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input logic branch_taken_ex_i, // branch taken signal
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input logic branch_set_i, // branch taken set signal
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input logic jump_set_i, // jump taken set signal
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input logic instr_multicyle_i, // multicycle instructions active
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// Interrupt Controller Signals
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input logic irq_req_ctrl_i,
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input logic [4:0] irq_id_ctrl_i,
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input logic m_IE_i, // interrupt enable bit from CSR (M mode)
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output logic irq_ack_o,
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output logic [4:0] irq_id_o,
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output logic [5:0] exc_cause_o,
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output logic exc_ack_o,
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output logic exc_kill_o,
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output logic csr_save_if_o,
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output logic csr_save_id_o,
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output logic [5:0] csr_cause_o,
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output logic csr_restore_mret_id_o,
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output logic csr_save_cause_o,
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// Debug Signals
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input logic dbg_req_i, // a trap was hit, so we have to flush EX and WB
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output logic dbg_ack_o, // we stopped and give control to debug now
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input logic dbg_stall_i, // Pipeline stall is requested
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input logic dbg_jump_req_i, // Change PC to value from debug unit
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input logic [DBG_SETS_W-1:0] dbg_settings_i,
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output logic dbg_trap_o,
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// forwarding signals
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output logic [1:0] operand_a_fw_mux_sel_o, // regfile ra data selector form ID stage
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// stall signals
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output logic halt_if_o,
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output logic halt_id_o,
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input logic id_ready_i, // ID stage is ready
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// Performance Counters
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output logic perf_jump_o, // we are executing a jump instruction (j, jr, jal, jalr)
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output logic perf_tbranch_o // we are executing a taken branch instruction
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);
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// FSM state encoding
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enum logic [3:0] { RESET, BOOT_SET, WAIT_SLEEP, SLEEP, FIRST_FETCH,
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DECODE, FLUSH, IRQ_TAKEN,
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DBG_SIGNAL, DBG_SIGNAL_SLEEP, DBG_WAIT, DBG_WAIT_BRANCH, DBG_WAIT_SLEEP } ctrl_fsm_cs, ctrl_fsm_ns;
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logic irq_enable_int;
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`ifndef SYNTHESIS
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// synopsys translate_off
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// make sure we are called later so that we do not generate messages for
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// glitches
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always_ff @(negedge clk)
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begin
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// print warning in case of decoding errors
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if (is_decoding_o && illegal_insn_i) begin
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$display("%t: Illegal instruction (core %0d) at PC 0x%h:", $time, zeroriscy_core.core_id_i,
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zeroriscy_id_stage.pc_id_i);
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end
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end
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// synopsys translate_on
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`endif
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////////////////////////////////////////////////////////////////////////////////////////////
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// ____ ___ ____ _____ ____ ___ _ _ _____ ____ ___ _ _ _____ ____ //
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// / ___/ _ \| _ \| ____| / ___/ _ \| \ | |_ _| _ \ / _ \| | | | | ____| _ \ //
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// | | | | | | |_) | _| | | | | | | \| | | | | |_) | | | | | | | | _| | |_) | //
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// | |__| |_| | _ <| |___ | |__| |_| | |\ | | | | _ <| |_| | |___| |___| |___| _ < //
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// \____\___/|_| \_\_____| \____\___/|_| \_| |_| |_| \_\\___/|_____|_____|_____|_| \_\ //
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// //
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////////////////////////////////////////////////////////////////////////////////////////////
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always_comb
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begin
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// Default values
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instr_req_o = 1'b1;
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exc_ack_o = 1'b0;
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exc_kill_o = 1'b0;
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csr_save_if_o = 1'b0;
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csr_save_id_o = 1'b0;
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csr_restore_mret_id_o = 1'b0;
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csr_save_cause_o = 1'b0;
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exc_cause_o = '0;
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exc_pc_mux_o = EXC_PC_IRQ;
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csr_cause_o = '0;
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pc_mux_o = PC_BOOT;
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pc_set_o = 1'b0;
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ctrl_fsm_ns = ctrl_fsm_cs;
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ctrl_busy_o = 1'b1;
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is_decoding_o = 1'b0;
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first_fetch_o = 1'b0;
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halt_if_o = 1'b0;
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halt_id_o = 1'b0;
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dbg_ack_o = 1'b0;
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irq_ack_o = 1'b0;
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irq_id_o = irq_id_ctrl_i;
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irq_enable_int = m_IE_i;
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// a trap towards the debug unit is generated when one of the
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// following conditions are true:
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// - ebreak instruction encountered
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// - single-stepping mode enabled
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// - illegal instruction exception and IIE bit is set
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// - IRQ and INTE bit is set and no exception is currently running
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// - Debuger requests halt
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dbg_trap_o = 1'b0;
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perf_tbranch_o = 1'b0;
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perf_jump_o = 1'b0;
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unique case (ctrl_fsm_cs)
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// We were just reset, wait for fetch_enable
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RESET:
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begin
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ctrl_busy_o = 1'b0;
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instr_req_o = 1'b0;
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if (fetch_enable_i == 1'b1)
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ctrl_fsm_ns = BOOT_SET;
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else if (dbg_req_i) begin
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// just go to debug even when we did not yet get a fetch enable
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// this means that the NPC will not be set yet
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ctrl_fsm_ns = DBG_SIGNAL;
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end
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end
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// copy boot address to instr fetch address
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BOOT_SET:
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begin
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instr_req_o = 1'b1;
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pc_mux_o = PC_BOOT;
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pc_set_o = 1'b1;
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ctrl_fsm_ns = FIRST_FETCH;
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end
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WAIT_SLEEP:
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begin
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ctrl_busy_o = 1'b0;
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instr_req_o = 1'b0;
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halt_if_o = 1'b1;
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halt_id_o = 1'b1;
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ctrl_fsm_ns = SLEEP;
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end
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// instruction in if_stage is already valid
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SLEEP:
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begin
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// we begin execution when either fetch_enable is high or an
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// interrupt has arrived
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ctrl_busy_o = 1'b0;
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instr_req_o = 1'b0;
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halt_if_o = 1'b1;
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halt_id_o = 1'b1;
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dbg_trap_o = dbg_settings_i[DBG_SETS_SSTE];
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if (dbg_req_i) begin
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// debug request, now we need to check if we should stay sleeping or
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// go to normal processing later
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if (fetch_enable_i || irq_req_ctrl_i)
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ctrl_fsm_ns = DBG_SIGNAL;
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else
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ctrl_fsm_ns = DBG_SIGNAL_SLEEP;
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end else begin
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// no debug request incoming, normal execution flow
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if (fetch_enable_i || irq_req_ctrl_i)
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begin
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ctrl_fsm_ns = FIRST_FETCH;
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end
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end
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end
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FIRST_FETCH:
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begin
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first_fetch_o = 1'b1;
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// Stall because of IF miss
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if ((id_ready_i == 1'b1) && (dbg_stall_i == 1'b0))
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begin
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ctrl_fsm_ns = DECODE;
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end
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if (irq_req_ctrl_i & irq_enable_int) begin
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// This assumes that the pipeline is always flushed before
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// going to sleep.
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ctrl_fsm_ns = IRQ_TAKEN;
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halt_if_o = 1'b1;
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halt_id_o = 1'b1;
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end
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end
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DECODE:
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begin
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is_decoding_o = 1'b0;
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// decode and execute instructions only if the current conditional
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// branch in the EX stage is either not taken, or there is no
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// conditional branch in the EX stage
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if (instr_valid_i)
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begin // now analyze the current instruction in the ID stage
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is_decoding_o = 1'b1;
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unique case (1'b1)
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branch_set_i: begin
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pc_mux_o = PC_JUMP;
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pc_set_o = 1'b1;
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perf_tbranch_o = 1'b1;
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dbg_trap_o = dbg_settings_i[DBG_SETS_SSTE];
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if (dbg_req_i)
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ctrl_fsm_ns = DBG_SIGNAL;
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end
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jump_set_i: begin
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pc_mux_o = PC_JUMP;
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pc_set_o = 1'b1;
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perf_jump_o = 1'b1;
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dbg_trap_o = dbg_settings_i[DBG_SETS_SSTE];
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end
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mret_insn_i | ecall_insn_i | pipe_flush_i | ebrk_insn_i | illegal_insn_i | csr_status_i: begin
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ctrl_fsm_ns = FLUSH;
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halt_if_o = 1'b1;
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halt_id_o = 1'b1;
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end
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default: begin
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dbg_trap_o = dbg_settings_i[DBG_SETS_SSTE];
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unique case (1'b1)
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irq_req_ctrl_i & irq_enable_int & ~instr_multicyle_i & ~branch_in_id_i: begin
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ctrl_fsm_ns = IRQ_TAKEN;
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halt_if_o = 1'b1;
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halt_id_o = 1'b1;
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end
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dbg_req_i & ~branch_taken_ex_i: begin
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halt_if_o = 1'b1;
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if (id_ready_i) begin
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ctrl_fsm_ns = DBG_SIGNAL;
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end
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end
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default:
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exc_kill_o = irq_req_ctrl_i & ~instr_multicyle_i & ~branch_in_id_i ? 1'b1 : 1'b0;
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endcase
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end
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endcase
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end
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else //~instr_valid_i
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begin
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if (irq_req_ctrl_i & irq_enable_int) begin
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ctrl_fsm_ns = IRQ_TAKEN;
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halt_if_o = 1'b1;
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halt_id_o = 1'b1;
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end
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end
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end
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// now we can signal to the debugger that our pipeline is empty and it
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// can examine our current state
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DBG_SIGNAL:
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begin
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dbg_ack_o = 1'b1;
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halt_if_o = 1'b1;
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ctrl_fsm_ns = DBG_WAIT;
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end
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DBG_SIGNAL_SLEEP:
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begin
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dbg_ack_o = 1'b1;
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halt_if_o = 1'b1;
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ctrl_fsm_ns = DBG_WAIT_SLEEP;
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end
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// The Debugger is active in this state
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// we wait until it is done and go back to SLEEP
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DBG_WAIT_SLEEP:
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begin
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halt_if_o = 1'b1;
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if (dbg_jump_req_i) begin
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pc_mux_o = PC_DBG_NPC;
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pc_set_o = 1'b1;
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ctrl_fsm_ns = DBG_WAIT;
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end
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if (dbg_stall_i == 1'b0) begin
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ctrl_fsm_ns = SLEEP;
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end
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end
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// The Debugger is active in this state
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// we wait until it is done and go back to DECODE
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DBG_WAIT:
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begin
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halt_if_o = 1'b1;
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if (dbg_jump_req_i) begin
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pc_mux_o = PC_DBG_NPC;
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pc_set_o = 1'b1;
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ctrl_fsm_ns = DBG_WAIT;
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end
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if (dbg_stall_i == 1'b0) begin
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ctrl_fsm_ns = DECODE;
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end
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end
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IRQ_TAKEN:
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begin
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pc_mux_o = PC_EXCEPTION;
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pc_set_o = 1'b1;
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exc_pc_mux_o = EXC_PC_IRQ;
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exc_cause_o = {1'b0,irq_id_ctrl_i};
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csr_save_cause_o = 1'b1;
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csr_cause_o = {1'b1,irq_id_ctrl_i};
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csr_save_if_o = 1'b1;
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irq_ack_o = 1'b1;
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exc_ack_o = 1'b1;
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ctrl_fsm_ns = DECODE;
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end
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// flush the pipeline, insert NOP
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FLUSH:
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begin
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halt_if_o = fetch_enable_i ? dbg_req_i : 1'b1;
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halt_id_o = 1'b1;
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ctrl_fsm_ns = dbg_req_i ? DBG_SIGNAL : DECODE;
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unique case(1'b1)
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ecall_insn_i: begin
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//ecall
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pc_mux_o = PC_EXCEPTION;
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pc_set_o = 1'b1;
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csr_save_id_o = 1'b1;
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csr_save_cause_o = 1'b1;
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exc_pc_mux_o = EXC_PC_ECALL;
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exc_cause_o = EXC_CAUSE_ECALL_MMODE;
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csr_cause_o = EXC_CAUSE_ECALL_MMODE;
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dbg_trap_o = dbg_settings_i[DBG_SETS_ECALL] | dbg_settings_i[DBG_SETS_SSTE];
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end
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illegal_insn_i: begin
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//exceptions
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pc_mux_o = PC_EXCEPTION;
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pc_set_o = 1'b1;
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csr_save_id_o = 1'b1;
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csr_save_cause_o = 1'b1;
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exc_pc_mux_o = EXC_PC_ILLINSN;
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exc_cause_o = EXC_CAUSE_ILLEGAL_INSN;
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csr_cause_o = EXC_CAUSE_ILLEGAL_INSN;
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dbg_trap_o = dbg_settings_i[DBG_SETS_EILL] | dbg_settings_i[DBG_SETS_SSTE];
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end
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mret_insn_i: begin
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//mret
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pc_mux_o = PC_ERET;
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pc_set_o = 1'b1;
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csr_restore_mret_id_o = 1'b1;
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dbg_trap_o = dbg_settings_i[DBG_SETS_SSTE];
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end
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ebrk_insn_i: begin
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dbg_trap_o = dbg_settings_i[DBG_SETS_EBRK] | dbg_settings_i[DBG_SETS_SSTE];;
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exc_cause_o = EXC_CAUSE_BREAKPOINT;
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end
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csr_status_i: begin
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dbg_trap_o = dbg_settings_i[DBG_SETS_SSTE];
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end
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pipe_flush_i: begin
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dbg_trap_o = dbg_settings_i[DBG_SETS_SSTE];
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end
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default:;
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endcase
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if(fetch_enable_i) begin
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if(dbg_req_i)
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ctrl_fsm_ns = DBG_SIGNAL;
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else
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ctrl_fsm_ns = DECODE;
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end else begin
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if(dbg_req_i)
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ctrl_fsm_ns = DBG_SIGNAL_SLEEP;
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else
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ctrl_fsm_ns = (mret_insn_i | pipe_flush_i) ? WAIT_SLEEP : DECODE;
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end
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end
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default: begin
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instr_req_o = 1'b0;
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ctrl_fsm_ns = RESET;
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end
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endcase
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end
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/////////////////////////////////////////////////////////////
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// ____ _ _ _ ____ _ _ //
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// / ___|| |_ __ _| | | / ___|___ _ __ | |_ _ __ ___ | | //
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// \___ \| __/ _` | | | | | / _ \| '_ \| __| '__/ _ \| | //
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// ___) | || (_| | | | | |__| (_) | | | | |_| | | (_) | | //
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// |____/ \__\__,_|_|_| \____\___/|_| |_|\__|_| \___/|_| //
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// //
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/////////////////////////////////////////////////////////////
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always_comb
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begin
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deassert_we_o = 1'b0;
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// deassert WE when the core is not decoding instructions
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if (~is_decoding_o)
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deassert_we_o = 1'b1;
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|
|
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// deassert WE in case of illegal instruction
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if (illegal_insn_i)
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deassert_we_o = 1'b1;
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end
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|
|
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// Forwarding control unit
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assign operand_a_fw_mux_sel_o = data_misaligned_i ? SEL_MISALIGNED : SEL_REGFILE;
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|
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// update registers
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always_ff @(posedge clk , negedge rst_n)
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begin : UPDATE_REGS
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if ( rst_n == 1'b0 )
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|
begin
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ctrl_fsm_cs <= RESET;
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//jump_done_q <= 1'b0;
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|
end
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else
|
|
begin
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ctrl_fsm_cs <= ctrl_fsm_ns;
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|
// clear when id is valid (no instruction incoming)
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//jump_done_q <= jump_done & (~id_ready_i);
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|
end
|
|
end
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//----------------------------------------------------------------------------
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// Assertions
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//----------------------------------------------------------------------------
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`ifndef VERILATOR
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|
assert property (
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@(posedge clk) (~(dbg_req_i & irq_req_ctrl_i)) ) else $warning("Both dbg_req_i and irq_req_ctrl_i are active");
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`endif
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endmodule // controller
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