ibex/examples/sw/simple_system/common
Canberk Topal 4b54d79fb4 [sw/fpga] coremark/link.ld update for FPGA sim
This commit updates link.ld RAM length to include max BRAM capacity
for Arty A7-35. It also changes coremark makefile to include a .vmem
output, which then can be used for FPGA implementations.

Signed-off-by: Canberk Topal <ctopal@lowrisc.org>
2021-08-03 16:51:16 +01:00
..
common.mk [sw] Fix GNU GCC toolchain component substitution for file path case. 2021-07-12 12:53:53 +01:00
crt0.S [examples] Add timer example to simple system 2020-01-10 10:18:09 +00:00
link.ld [sw/fpga] coremark/link.ld update for FPGA sim 2021-08-03 16:51:16 +01:00
simple_system_common.c [simple_system] Update CSR Access for LLVM and GCC 2020-09-22 16:57:14 +01:00
simple_system_common.h [sw/simple_system] Add PCOUNT_READ macro 2020-03-09 14:41:40 +00:00
simple_system_regs.h Make exiting from simple_system tests work with Spike 2020-03-02 15:45:47 +00:00