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35abca14ab
- Add a technology map for latches (only works with nandgate45 library at the moment) - Add a real latch-based clock gating cell - Update timing path reporting to differentiate between register and latch paths - Update summary results in README to reflect the latch-based numbers, plus add numbers for a micro-riscy-style (RV32EC) config Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
12 lines
303 B
Verilog
12 lines
303 B
Verilog
// Copyright lowRISC contributors.
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// Licensed under the Apache License, Version 2.0, see LICENSE for details.
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// SPDX-License-Identifier: Apache-2.0
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// Map latch primitives to a specific cell
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module $_DLATCH_P_ (input E, input D, output Q);
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DLH_X1 _TECHMAP_REPLACE_ (
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.G(E),
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.D(D),
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.Q(Q)
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);
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endmodule
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