Rupert Swarbrick fbe4e9da08 [verilator] Remove clock gating waiver and add extra warning ... The -Wwarn-IMPERFECTSCH flag is suggested in the Verilator docs (to help spot if we get a clock gating hint wrong). The waiver is no longer needed because we now add the relevant hint in the RTL (vendored in prim_generic_clock_gating.sv from OpenTitan).		2021-01-25 10:25:26 +00:00
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fpga/artya7	[doc] Fix broken link to examples description	2020-10-02 15:03:19 +01:00
simple_system	[verilator] Remove clock gating waiver and add extra warning	2021-01-25 10:25:26 +00:00
sw	[simple-system] Add missing linker sections	2020-09-23 14:28:31 +01:00