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7d61def943
Update code from upstream repository https://github.com/lowRISC/opentitan to revision f29a0f7a7115e03fba734b1c00691c253aceb07e. The list of OpenTitan changes that are merged in appears at the bottom of the commit. There are some manual changes needed to adapt the code to work with these changes. - The ICache monitors need some extra types to adapt to the (rather odd) data model that the OpenTitan dv_lib code now uses, where a monitor needs to know an agent's associated sequence type. - Verilator simulations now use MemArea slightly differently OpenTitan changes: * [dv] Allow monitor items to have different types from sequence items (Rupert Swarbrick) * [dvsim] Fix primary_cfg handling (Srikrishna Iyer) * [dvsim] Deal with non unicode chars in log files (Srikrishna Iyer) * [dvsim] Added common build fail patterns (Srikrishna Iyer) * [dvsim] Minot cleanup to the lint flow (Srikrishna Iyer) * [dvsim] Minor cleanups to to formal flow (Srikrishna Iyer) * [dvsim] Fixes to UNR and cov analysis flows (Srikrishna Iyer) * [dvsim] Very minor cleanup of Deploy class (Srikrishna Iyer) * [dvsim] LsfLauncher report early errors as F (Srikrishna Iyer) * [dvsim] Minor fix in clean_odirs function (Srikrishna Iyer) * [chip dv] Set +sw_images as comma-separated list (Srikrishna Iyer) * [flash_ctrl] Split tl intefaces for flash_ctrl and prim_flash_cfg (Timothy Chen) * [keymgr] Fix input value checks (Timothy Chen) * [formal/script] Update generic formal flow naming from `fpv` to `formal` (Cindy Chen) * [top, prim] Address wmask and data width mismatch issue (Timothy Chen) * [dvsim] Add GUI mode for running simulations (Srikrishna Iyer) * [dv] Fix reg backdoor (Weicai Yang) * [dpi] Make an "ECC32" flavour of MemArea (Rupert Swarbrick) * [uvmdvgen] Fix has_interrupts in env_cfg (Cindy Chen) * [dvsim] Keep dependencies list (Srikrishna Iyer) * [prim_prince] Reverse the k0||k1 mapping to match with the paper (Michael Schaffner) * [dvsim] Fix printing of last 10 lines (Srikrishna Iyer) * [primgen] Minor fix to enable types with underscores (Michael Schaffner) * [dvsim] Prevent command echo suppression (Srikrishna Iyer) * [dvsim] Spot fixes for LSF and internal launcher (Srikrishna Iyer) * [sva] csr assertion dependency update (Cindy Chen) * [memutil] Change DpiMemUtil so that it no longer owns MemAreas (Rupert Swarbrick) * [memutil] Factor out MemArea as a class (Rupert Swarbrick) * [prim] Split out PRESENT and PRINCE support from prim:all (Rupert Swarbrick) * [fpv/otp_ctrl] Disable assertions due to lc_esc_en (Cindy Chen) * [prim_prince] Annotate some arrays to avoid UNOPTFLAT warnings (Rupert Swarbrick) * [top] Hook up latest ast ports and complete a few other integration (Timothy Chen) * Eliminate `#pragma once` in favor of include guards (Chris Frantz) * [sw,dv] Update headers to pass fix_include_guards.py (Alex Bradbury) * [xbar/dv] Fix assertion error due to short reset (Weicai Yang) * [sram] Add memory initialization (Timothy Chen) * [uvmdvgen] Update links in checklist template (Philipp Wagner) * [dv/uvmdvgen] Add comment for testplan (Cindy Chen) * [dv/top_earlgrey] chip csr_aliasing timeout (Cindy Chen) * [dvsim] Cosmetic updates to launcher methods (Srikrishna Iyer) * [dv] Update csr_wr to support field write (Weicai Yang) * [dv/common] Fix regression warnings (Cindy Chen) * [dv] Get blocks with multiple device interfaces working with chip DV (Rupert Swarbrick) * [doc] Use relative links in Hjson-related shortcodes (Philipp Wagner) * [dvsim] minor enhancement to clean_odir (Srikrishna Iyer) * [dvsim] Statically display jobs' status (Srikrishna Iyer) * [dvsim] Do weighted scheduling of jobs (Srikrishna Iyer) * [dvsim] Schedule jobs by dependency (Srikrishna Iyer) * [dv] Xcelium UNR typo (Srikrishna Iyer) * [dvsim] Implement LsfLauncher (Srikrishna Iyer) * [dv/chip] solve same_csr_outstanding_timeout (Cindy Chen) * [dv] make dv_base_agent work for high-level agent (Weicai Yang) * [tools/dv] added UNR flow for xcelium (Rasmus Madsen) * [prim] Split prim:subreg out of prim:all (Rupert Swarbrick) * [prim] Split prim_alert_* out of prim:all (Rupert Swarbrick) * [prim] Split out fifos into a prim_fifo core (Rupert Swarbrick) * [prim] Split out arbiters into a prim_arbiter core (Rupert Swarbrick) * [prim] Make prim:flop_2sync depend on prim:flop (Rupert Swarbrick) Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>
55 lines
1.7 KiB
C++
55 lines
1.7 KiB
C++
// Copyright lowRISC contributors.
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// Licensed under the Apache License, Version 2.0, see LICENSE for details.
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// SPDX-License-Identifier: Apache-2.0
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#include <fstream>
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#include <iostream>
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#include "ibex_pcounts.h"
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#include "verilated_toplevel.h"
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#include "verilator_memutil.h"
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#include "verilator_sim_ctrl.h"
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int main(int argc, char **argv) {
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ibex_simple_system top;
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VerilatorMemUtil memutil;
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VerilatorSimCtrl &simctrl = VerilatorSimCtrl::GetInstance();
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simctrl.SetTop(&top, &top.IO_CLK, &top.IO_RST_N,
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VerilatorSimCtrlFlags::ResetPolarityNegative);
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MemArea ram("TOP.ibex_simple_system.u_ram.u_ram.gen_generic.u_impl_generic",
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1024 * 1024 / 4, 4);
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memutil.RegisterMemoryArea("ram", 0x0, &ram);
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simctrl.RegisterExtension(&memutil);
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bool exit_app = false;
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int ret_code = simctrl.ParseCommandArgs(argc, argv, exit_app);
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if (exit_app) {
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return ret_code;
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}
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std::cout << "Simulation of Ibex" << std::endl
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<< "==================" << std::endl
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<< std::endl;
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simctrl.RunSimulation();
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if (!simctrl.WasSimulationSuccessful()) {
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return 1;
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}
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// Set the scope to the root scope, the ibex_pcount_string function otherwise
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// doesn't know the scope itself. Could be moved to ibex_pcount_string, but
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// would require a way to set the scope name from here, similar to MemUtil.
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svSetScope(svGetScopeFromName("TOP.ibex_simple_system"));
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std::cout << "\nPerformance Counters" << std::endl
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<< "====================" << std::endl;
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std::cout << ibex_pcount_string(false);
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std::ofstream pcount_csv("ibex_simple_system_pcount.csv");
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pcount_csv << ibex_pcount_string(true);
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return 0;
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}
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