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9bd09c0b74
The clock gating primitive is now a dependency of the lowrisc:ibex:ibex_core file directly and only used in there, we can remove it from the simulation or FPGA dependency collections.
17 lines
448 B
Text
17 lines
448 B
Text
CAPI=2:
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# Copyright lowRISC contributors.
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# Licensed under the Apache License, Version 2.0, see LICENSE for details.
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# SPDX-License-Identifier: Apache-2.0
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name: "lowrisc:ibex:fpga_xilinx_shared"
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description: "Collection of useful RTL for Xilinx based examples"
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filesets:
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files_sv:
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files:
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- rtl/fpga/xilinx/clkgen_xil7series.sv
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- rtl/ram_1p.sv
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file_type: systemVerilogSource
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targets:
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default:
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filesets:
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- files_sv
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