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https://github.com/lowRISC/ibex.git
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f025236a22
- Fixes #288 - Add missing grant qualification to stop incorrect address updates - Make RTL robust to spurious rvalid signalling - Make sure a request is held until granted - Remove incorrect assertion
234 lines
8.9 KiB
Systemverilog
234 lines
8.9 KiB
Systemverilog
// Copyright lowRISC contributors.
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// Copyright 2018 ETH Zurich and University of Bologna, see also CREDITS.md.
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// Licensed under the Apache License, Version 2.0, see LICENSE for details.
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// SPDX-License-Identifier: Apache-2.0
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/**
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* Prefetcher Buffer for 32 bit memory interface
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*
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* Prefetch Buffer that caches instructions. This cuts overly long critical
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* paths to the instruction cache.
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*/
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module ibex_prefetch_buffer (
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input logic clk_i,
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input logic rst_ni,
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input logic req_i,
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input logic branch_i,
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input logic [31:0] addr_i,
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input logic ready_i,
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output logic valid_o,
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output logic [31:0] rdata_o,
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output logic [31:0] addr_o,
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output logic err_o,
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// goes to instruction memory / instruction cache
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output logic instr_req_o,
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input logic instr_gnt_i,
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output logic [31:0] instr_addr_o,
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input logic [31:0] instr_rdata_i,
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input logic instr_err_i,
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input logic instr_pmp_err_i,
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input logic instr_rvalid_i,
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// Prefetch Buffer Status
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output logic busy_o
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);
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// Changes to the address flops would be required for > 2 outstanding requests
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localparam int unsigned NUM_REQS = 2;
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logic valid_req;
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logic valid_req_d, valid_req_q;
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logic hold_addr_d, hold_addr_q;
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logic gnt_or_pmp_err, rvalid_or_pmp_err;
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logic [NUM_REQS-1:0] rdata_outstanding_n, rdata_outstanding_s, rdata_outstanding_q;
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logic [NUM_REQS-1:0] branch_abort_n, branch_abort_s, branch_abort_q;
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logic [31:0] instr_addr_q, fetch_addr;
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logic [31:0] instr_addr, instr_addr_w_aligned;
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logic addr_valid;
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logic pmp_err_q;
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logic instr_or_pmp_err;
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logic fifo_valid;
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logic fifo_ready;
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logic fifo_clear;
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////////////////////////////
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// Prefetch buffer status //
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////////////////////////////
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assign busy_o = (|rdata_outstanding_q) | instr_req_o;
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//////////////////////////////////////////////
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// Fetch fifo - consumes addresses and data //
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//////////////////////////////////////////////
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// Instruction fetch errors are valid on the data phase of a request
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// PMP errors are generated in the address phase, and registered into a fake data phase
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assign instr_or_pmp_err = instr_err_i | pmp_err_q;
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// A branch will invalidate any previously fetched instructions
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assign fifo_clear = branch_i;
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ibex_fetch_fifo fifo_i (
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.clk_i ( clk_i ),
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.rst_ni ( rst_ni ),
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.clear_i ( fifo_clear ),
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.in_valid_i ( fifo_valid ),
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.in_addr_i ( instr_addr_q ),
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.in_rdata_i ( instr_rdata_i ),
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.in_err_i ( instr_or_pmp_err ),
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.in_ready_o ( fifo_ready ),
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.out_valid_o ( valid_o ),
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.out_ready_i ( ready_i ),
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.out_rdata_o ( rdata_o ),
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.out_addr_o ( addr_o ),
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.out_err_o ( err_o )
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);
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//////////////
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// Requests //
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//////////////
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// Make a new request any time there is space in the FIFO, and space in the request queue
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assign valid_req = valid_req_q | (req_i & (fifo_ready | branch_i) & (~&rdata_outstanding_q));
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// If a request address triggers a PMP error, the external bus request is suppressed. We might
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// therefore never receive a grant for such a request. The grant is faked in this case to make
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// sure the request proceeds and the error is pushed to the FIFO.
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// We always use the registered version of the signal since it will be held stable throughout
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// the request, and the penalty of waiting for an extra cycle to consume the error is irrelevant.
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// A branch could update the address (and therefore data_pmp_err_i) on the cycle a request is
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// issued, in which case we must ignore the registered version.
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assign gnt_or_pmp_err = instr_gnt_i | (pmp_err_q & ~branch_i);
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// As with the grant, the rvalid must be faked for a PMP error, since the request was suppressed.
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// Since the pmp_err_q flop is only updated when the address updates, it will always point to the
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// PMP error status of the oldest outstanding request
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assign rvalid_or_pmp_err = rdata_outstanding_q[0] & (instr_rvalid_i | pmp_err_q);
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// Hold the request stable for requests that didn't get granted
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assign valid_req_d = valid_req & ~instr_gnt_i;
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// Hold the address stable for requests that couldn't be issued, or didn't get granted.
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// This is different to valid_req_q since there are cases where we must use addr+4 for
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// an ungranted request rather than addr_q (where addr_q has not been updated).
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assign hold_addr_d = (branch_i | hold_addr_q) & ~(valid_req & instr_gnt_i);
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////////////////
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// Fetch addr //
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////////////////
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// The address flop is used to hold the address steady for ungranted requests and also to
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// push the address to the FIFO for completed requests. For this reason, the address is only
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// updated once a request is the oldest outstanding to ensure that newer requests do not
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// overwrite the addresses of older ones. Branches are an exception to this, since all older
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// addresses will be discarded due to the branch.
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// Update the addr_q flop on any branch, or
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assign addr_valid = branch_i |
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// A new request which will be the oldest, or
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(valid_req & instr_gnt_i & ~rdata_outstanding_q[0]) |
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// each time a valid request becomes the oldest
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(rvalid_or_pmp_err & ~branch_abort_q[0] &
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((valid_req & instr_gnt_i) | rdata_outstanding_q[1]));
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// Fetch the next word-aligned instruction address
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assign fetch_addr = {instr_addr_q[31:2], 2'b00} + 32'd4;
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// Address mux
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assign instr_addr = branch_i ? addr_i :
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hold_addr_q ? instr_addr_q :
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fetch_addr;
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assign instr_addr_w_aligned = {instr_addr[31:2], 2'b00};
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///////////////////////////////
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// Request outstanding queue //
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///////////////////////////////
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for (genvar i = 0; i < NUM_REQS; i++) begin : g_outstanding_reqs
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// Request 0 (always the oldest outstanding request)
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if (i == 0) begin : g_req0
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// A request becomes outstanding once granted, and is cleared once the rvalid is received.
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// Outstanding requests shift down the queue towards entry 0. Entry 0 considers the PMP
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// error cases while newer entries do not (pmp_err_q is only valid for entry 0)
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assign rdata_outstanding_n[i] = (valid_req & gnt_or_pmp_err) |
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rdata_outstanding_q[i];
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// If a branch is received at any point while a request is outstanding, it must be tracked
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// to ensure we discard the data once received
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assign branch_abort_n[i] = (branch_i & rdata_outstanding_q[i]) | branch_abort_q[i];
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end else begin : g_reqtop
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assign rdata_outstanding_n[i] = (valid_req & instr_gnt_i &
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(&rdata_outstanding_q[i-1:0])) |
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rdata_outstanding_q[i];
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assign branch_abort_n[i] = (branch_i & rdata_outstanding_q[i]) | branch_abort_q[i];
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end
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end
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// Shift the entries down on each instr_rvalid_i
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assign rdata_outstanding_s = rvalid_or_pmp_err ? {1'b0,rdata_outstanding_n[NUM_REQS-1:1]} :
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rdata_outstanding_n;
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assign branch_abort_s = rvalid_or_pmp_err ? {1'b0,branch_abort_n[NUM_REQS-1:1]} :
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branch_abort_n;
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// Push a new entry to the FIFO once complete (and not aborted by a branch)
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assign fifo_valid = rvalid_or_pmp_err & ~branch_abort_q[0];
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///////////////
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// Registers //
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///////////////
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always_ff @(posedge clk_i or negedge rst_ni) begin
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if (!rst_ni) begin
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valid_req_q <= 1'b0;
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hold_addr_q <= 1'b0;
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rdata_outstanding_q <= 'b0;
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branch_abort_q <= 'b0;
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end else begin
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valid_req_q <= valid_req_d;
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hold_addr_q <= hold_addr_d;
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rdata_outstanding_q <= rdata_outstanding_s;
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branch_abort_q <= branch_abort_s;
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end
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end
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// CPU resets with a branch, so no need to reset these
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always_ff @(posedge clk_i) begin
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if (addr_valid) begin
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instr_addr_q <= instr_addr;
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pmp_err_q <= instr_pmp_err_i;
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end
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end
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/////////////
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// Outputs //
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/////////////
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assign instr_req_o = valid_req;
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assign instr_addr_o = instr_addr_w_aligned;
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////////////////
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// Assertions //
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////////////////
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`ifndef VERILATOR
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// Code changes required to support > 2 outstanding requests
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assert property (
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@(posedge clk_i) disable iff (!rst_ni)
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(NUM_REQS <= 2) );
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`endif
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endmodule
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