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Check that the number of cycles are always as specified for the current configuration for data independent operations. The required input signals for each arithmetic operation are split into different files which are included into the testbench. For each combination of operation and configured configuration (slow/fast/single) a define stores the number of cycles in a separate file. A target exists for each combination. For a convenient execution the targets are grouped together in a makefile. The implementation is based on the formal/icache checks. For the selection of the single cycle multiplication with the fast multiplication the parameter is set directly to the enum integer value.
77 lines
2.5 KiB
Systemverilog
77 lines
2.5 KiB
Systemverilog
// Copyright lowRISC contributors.
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// Licensed under the Apache License, Version 2.0, see LICENSE for details.
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// SPDX-License-Identifier: Apache-2.0
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// A formal testbench for the ICache. This gets bound into the actual ICache DUT.
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`include "prim_assert.sv"
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module formal_tb (
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// Top-level ports
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input logic clk_i,
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input logic rst_ni,
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input logic mult_en_i, // dynamic enable signal, for FSM control
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input logic div_en_i, // dynamic enable signal, for FSM control
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input logic mult_sel_i, // static decoder input, for data muxes
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input logic div_sel_i, // static decoder input, for data muxes
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input ibex_pkg::md_op_e operator_i,
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input logic [1:0] signed_mode_i,
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input logic [31:0] op_a_i,
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input logic [31:0] op_b_i,
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input logic [33:0] alu_adder_ext_i,
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input logic [31:0] alu_adder_i,
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input logic equal_to_zero_i,
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input logic data_ind_timing_i,
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input logic [32:0] alu_operand_a_o,
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input logic [32:0] alu_operand_b_o,
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input logic [33:0] imd_val_q_i[1:0],
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input logic [33:0] imd_val_d_o[1:0],
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input logic [1:0] imd_val_we_o,
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input logic multdiv_ready_id_i,
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input logic [31:0] multdiv_result_o,
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input logic valid_o
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);
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import ibex_pkg::*;
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logic [2:0] f_startup_count = 3'd0;
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always_ff @(posedge clk_i) begin : reset_assertion
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f_startup_count <= f_startup_count + ((f_startup_count == 3'd5) ? 3'd0 : 3'd1);
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// Assume that rst_ni is low for the first cycle and not true after that.
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assume (~((f_startup_count == 3'd0) ^ ~rst_ni));
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end
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`include "multdiv_operation.svh"
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// Defines with DATA_IND_OP_COUNT the number of cycles the current check must have.
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`include "multdiv_check.svh"
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logic [5:0] f_operation_count = 6'd0;
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logic checked = 1'b0;
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always_ff @(posedge clk_i) begin : count_assertion
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if (f_startup_count >= 3'd1) begin
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f_operation_count <= f_operation_count + 1;
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end
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end
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always_ff @(posedge clk_i) begin : check
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if (!checked && (valid_o || (f_operation_count == DATA_IND_OP_COUNT))) begin
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checked <= 1'b1;
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assert (valid_o && (f_operation_count == DATA_IND_OP_COUNT));
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assume (multdiv_ready_id_i);
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end
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end
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always_comb begin
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if (f_operation_count > DATA_IND_OP_COUNT) begin
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assert (checked);
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end
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end
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endmodule
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