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Check that the number of cycles are always as specified for the current configuration for data independent operations. The required input signals for each arithmetic operation are split into different files which are included into the testbench. For each combination of operation and configured configuration (slow/fast/single) a define stores the number of cycles in a separate file. A target exists for each combination. For a convenient execution the targets are grouped together in a makefile. The implementation is based on the formal/icache checks. For the selection of the single cycle multiplication with the fast multiplication the parameter is set directly to the enum integer value.
21 lines
585 B
Systemverilog
21 lines
585 B
Systemverilog
// Copyright lowRISC contributors.
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// Licensed under the Apache License, Version 2.0, see LICENSE for details.
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// SPDX-License-Identifier: Apache-2.0
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always_comb begin
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// Formal prove only for data independent timing
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assume (data_ind_timing_i);
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assume(~mult_sel_i);
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assume(~mult_en_i);
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if (f_startup_count >= 3'd2) begin
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// Enable signal must be asserted in order for the state machine to advance
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assume (div_en_i);
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assume (div_sel_i);
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assume (operator_i == ibex_pkg::MD_OP_REM);
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end else begin
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assume (~div_en_i);
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assume (~div_sel_i);
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end
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end
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