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1553636a7d
Check that the number of cycles are always as specified for the current configuration for data independent operations. The required input signals for each arithmetic operation are split into different files which are included into the testbench. For each combination of operation and configured configuration (slow/fast/single) a define stores the number of cycles in a separate file. A target exists for each combination. For a convenient execution the targets are grouped together in a makefile. The implementation is based on the formal/icache checks. For the selection of the single cycle multiplication with the fast multiplication the parameter is set directly to the enum integer value.
374 lines
13 KiB
Systemverilog
374 lines
13 KiB
Systemverilog
// Copyright lowRISC contributors.
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// Copyright 2018 ETH Zurich and University of Bologna, see also CREDITS.md.
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// Licensed under the Apache License, Version 2.0, see LICENSE for details.
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// SPDX-License-Identifier: Apache-2.0
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/**
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* Slow Multiplier and Division
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*
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* Baugh-Wooley multiplier and Long Division
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*/
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`include "prim_assert.sv"
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module ibex_multdiv_slow
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(
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input logic clk_i,
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input logic rst_ni,
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input logic mult_en_i, // dynamic enable signal, for FSM control
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input logic div_en_i, // dynamic enable signal, for FSM control
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input logic mult_sel_i, // static decoder output, for data muxes
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input logic div_sel_i, // static decoder output, for data muxes
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input ibex_pkg::md_op_e operator_i,
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input logic [1:0] signed_mode_i,
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input logic [31:0] op_a_i,
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input logic [31:0] op_b_i,
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input logic [33:0] alu_adder_ext_i,
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input logic [31:0] alu_adder_i,
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input logic equal_to_zero_i,
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input logic data_ind_timing_i,
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output logic [32:0] alu_operand_a_o,
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output logic [32:0] alu_operand_b_o,
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input logic [33:0] imd_val_q_i[2],
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output logic [33:0] imd_val_d_o[2],
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output logic [1:0] imd_val_we_o,
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input logic multdiv_ready_id_i,
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output logic [31:0] multdiv_result_o,
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output logic valid_o
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);
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import ibex_pkg::*;
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typedef enum logic [2:0] {
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MD_IDLE, MD_ABS_A, MD_ABS_B, MD_COMP, MD_LAST, MD_CHANGE_SIGN, MD_FINISH
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} md_fsm_e;
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md_fsm_e md_state_q, md_state_d;
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logic [32:0] accum_window_q, accum_window_d;
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logic unused_imd_val0;
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logic [ 1:0] unused_imd_val1;
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logic [32:0] res_adder_l;
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logic [32:0] res_adder_h;
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logic [ 4:0] multdiv_count_q, multdiv_count_d;
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logic [32:0] op_b_shift_q, op_b_shift_d;
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logic [32:0] op_a_shift_q, op_a_shift_d;
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logic [32:0] op_a_ext, op_b_ext;
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logic [32:0] one_shift;
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logic [32:0] op_a_bw_pp, op_a_bw_last_pp;
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logic [31:0] b_0;
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logic sign_a, sign_b;
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logic [32:0] next_quotient;
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logic [31:0] next_remainder;
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logic [31:0] op_numerator_q, op_numerator_d;
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logic is_greater_equal;
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logic div_change_sign, rem_change_sign;
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logic div_by_zero_d, div_by_zero_q;
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logic multdiv_hold;
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logic multdiv_en;
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// (accum_window_q + op_a_shift_q)
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assign res_adder_l = alu_adder_ext_i[32:0];
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// (accum_window_q + op_a_shift_q)>>1
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assign res_adder_h = alu_adder_ext_i[33:1];
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/////////////////////
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// ALU Operand MUX //
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/////////////////////
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// Intermediate value register shared with ALU
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assign imd_val_d_o[0] = {1'b0,accum_window_d};
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assign imd_val_we_o[0] = ~multdiv_hold;
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assign accum_window_q = imd_val_q_i[0][32:0];
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assign unused_imd_val0 = imd_val_q_i[0][33];
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assign imd_val_d_o[1] = {2'b00, op_numerator_d};
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assign imd_val_we_o[1] = multdiv_en;
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assign op_numerator_q = imd_val_q_i[1][31:0];
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assign unused_imd_val1 = imd_val_q_i[1][33:32];
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always_comb begin
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alu_operand_a_o = accum_window_q;
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unique case(operator_i)
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MD_OP_MULL: begin
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alu_operand_b_o = op_a_bw_pp;
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end
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MD_OP_MULH: begin
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alu_operand_b_o = (md_state_q == MD_LAST) ? op_a_bw_last_pp : op_a_bw_pp;
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end
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MD_OP_DIV,
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MD_OP_REM: begin
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unique case(md_state_q)
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MD_IDLE: begin
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// 0 - B = 0 iff B == 0
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alu_operand_a_o = {32'h0 , 1'b1};
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alu_operand_b_o = {~op_b_i, 1'b1};
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end
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MD_ABS_A: begin
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// ABS(A) = 0 - A
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alu_operand_a_o = {32'h0 , 1'b1};
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alu_operand_b_o = {~op_a_i, 1'b1};
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end
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MD_ABS_B: begin
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// ABS(B) = 0 - B
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alu_operand_a_o = {32'h0 , 1'b1};
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alu_operand_b_o = {~op_b_i, 1'b1};
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end
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MD_CHANGE_SIGN: begin
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// ABS(Quotient) = 0 - Quotient (or Reminder)
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alu_operand_a_o = {32'h0 , 1'b1};
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alu_operand_b_o = {~accum_window_q[31:0], 1'b1};
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end
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default: begin
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// Division
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alu_operand_a_o = {accum_window_q[31:0], 1'b1}; // it contains the remainder
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alu_operand_b_o = {~op_b_shift_q[31:0], 1'b1}; // -denominator two's compliment
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end
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endcase
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end
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default: begin
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alu_operand_a_o = accum_window_q;
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alu_operand_b_o = {~op_b_shift_q[31:0], 1'b1};
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end
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endcase
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end
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// Multiplier partial product calculation
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assign b_0 = {32{op_b_shift_q[0]}};
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assign op_a_bw_pp = { ~(op_a_shift_q[32] & op_b_shift_q[0]), (op_a_shift_q[31:0] & b_0) };
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assign op_a_bw_last_pp = { (op_a_shift_q[32] & op_b_shift_q[0]), ~(op_a_shift_q[31:0] & b_0) };
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// Sign extend the input operands
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assign sign_a = op_a_i[31] & signed_mode_i[0];
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assign sign_b = op_b_i[31] & signed_mode_i[1];
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assign op_a_ext = {sign_a, op_a_i};
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assign op_b_ext = {sign_b, op_b_i};
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// Divider calculations
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// The adder in the ALU computes Remainder - Divisor. If Remainder - Divisor >= 0,
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// is_greater_equal is true, the next Remainder is the subtraction result and the Quotient
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// multdiv_count_q-th bit is set to 1.
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assign is_greater_equal = (accum_window_q[31] == op_b_shift_q[31]) ?
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~res_adder_h[31] : accum_window_q[31];
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assign one_shift = {32'b0, 1'b1} << multdiv_count_q;
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assign next_remainder = is_greater_equal ? res_adder_h[31:0] : accum_window_q[31:0];
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assign next_quotient = is_greater_equal ? op_a_shift_q | one_shift : op_a_shift_q;
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assign div_change_sign = (sign_a ^ sign_b) & ~div_by_zero_q;
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assign rem_change_sign = sign_a;
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always_comb begin
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multdiv_count_d = multdiv_count_q;
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accum_window_d = accum_window_q;
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op_b_shift_d = op_b_shift_q;
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op_a_shift_d = op_a_shift_q;
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op_numerator_d = op_numerator_q;
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md_state_d = md_state_q;
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multdiv_hold = 1'b0;
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div_by_zero_d = div_by_zero_q;
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if (mult_sel_i || div_sel_i) begin
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unique case(md_state_q)
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MD_IDLE: begin
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unique case(operator_i)
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MD_OP_MULL: begin
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op_a_shift_d = op_a_ext << 1;
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accum_window_d = { ~(op_a_ext[32] & op_b_i[0]),
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op_a_ext[31:0] & {32{op_b_i[0]}} };
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op_b_shift_d = op_b_ext >> 1;
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// Proceed with multiplication by 0/1 in data-independent time mode
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md_state_d = (!data_ind_timing_i && ((op_b_ext >> 1) == 0)) ? MD_LAST : MD_COMP;
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end
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MD_OP_MULH: begin
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op_a_shift_d = op_a_ext;
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accum_window_d = { 1'b1, ~(op_a_ext[32] & op_b_i[0]),
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op_a_ext[31:1] & {31{op_b_i[0]}} };
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op_b_shift_d = op_b_ext >> 1;
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md_state_d = MD_COMP;
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end
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MD_OP_DIV: begin
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// Check if the denominator is 0
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// quotient for division by 0 is specified to be -1
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// Note with data-independent time option, the full divide operation will proceed as
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// normal and will naturally return -1
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accum_window_d = {33{1'b1}};
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md_state_d = (!data_ind_timing_i && equal_to_zero_i) ? MD_FINISH : MD_ABS_A;
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// Record that this is a div by zero to stop the sign change at the end of the
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// division (in data_ind_timing mode).
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div_by_zero_d = equal_to_zero_i;
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end
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MD_OP_REM: begin
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// Check if the denominator is 0
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// remainder for division by 0 is specified to be the numerator (operand a)
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// Note with data-independent time option, the full divide operation will proceed as
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// normal and will naturally return operand a
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accum_window_d = op_a_ext;
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md_state_d = (!data_ind_timing_i && equal_to_zero_i) ? MD_FINISH : MD_ABS_A;
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end
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default:;
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endcase
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multdiv_count_d = 5'd31;
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end
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MD_ABS_A: begin
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// quotient
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op_a_shift_d = '0;
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// A abs value
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op_numerator_d = sign_a ? alu_adder_i : op_a_i;
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md_state_d = MD_ABS_B;
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end
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MD_ABS_B: begin
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// remainder
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accum_window_d = {32'h0,op_numerator_q[31]};
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// B abs value
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op_b_shift_d = sign_b ? {1'b0,alu_adder_i} : {1'b0,op_b_i};
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md_state_d = MD_COMP;
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end
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MD_COMP: begin
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multdiv_count_d = multdiv_count_q - 5'h1;
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unique case(operator_i)
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MD_OP_MULL: begin
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accum_window_d = res_adder_l;
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op_a_shift_d = op_a_shift_q << 1;
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op_b_shift_d = op_b_shift_q >> 1;
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// Multiplication is complete once op_b is zero, unless in data_ind_timing mode where
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// the maximum possible shift-add operations will be completed regardless of op_b
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md_state_d = ((!data_ind_timing_i && (op_b_shift_d == 0)) ||
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(multdiv_count_q == 5'd1)) ? MD_LAST : MD_COMP;
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end
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MD_OP_MULH: begin
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accum_window_d = res_adder_h;
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op_a_shift_d = op_a_shift_q;
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op_b_shift_d = op_b_shift_q >> 1;
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md_state_d = (multdiv_count_q == 5'd1) ? MD_LAST : MD_COMP;
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end
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MD_OP_DIV,
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MD_OP_REM: begin
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accum_window_d = {next_remainder[31:0], op_numerator_q[multdiv_count_d]};
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op_a_shift_d = next_quotient;
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md_state_d = (multdiv_count_q == 5'd1) ? MD_LAST : MD_COMP;
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end
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default: ;
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endcase
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end
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MD_LAST: begin
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unique case(operator_i)
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MD_OP_MULL: begin
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accum_window_d = res_adder_l;
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// Note no state transition will occur if multdiv_hold is set
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md_state_d = MD_IDLE;
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multdiv_hold = ~multdiv_ready_id_i;
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end
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MD_OP_MULH: begin
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accum_window_d = res_adder_l;
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md_state_d = MD_IDLE;
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// Note no state transition will occur if multdiv_hold is set
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md_state_d = MD_IDLE;
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multdiv_hold = ~multdiv_ready_id_i;
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end
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MD_OP_DIV: begin
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// this time we save the quotient in accum_window_q since we do not need anymore the
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// remainder
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accum_window_d = next_quotient;
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md_state_d = MD_CHANGE_SIGN;
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end
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MD_OP_REM: begin
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// this time we do not save the quotient anymore since we need only the remainder
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accum_window_d = {1'b0, next_remainder[31:0]};
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md_state_d = MD_CHANGE_SIGN;
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end
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default: ;
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endcase
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end
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MD_CHANGE_SIGN: begin
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md_state_d = MD_FINISH;
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unique case(operator_i)
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MD_OP_DIV:
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accum_window_d = div_change_sign ? {1'b0,alu_adder_i} : accum_window_q;
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MD_OP_REM:
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accum_window_d = rem_change_sign ? {1'b0,alu_adder_i} : accum_window_q;
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default: ;
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endcase
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end
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MD_FINISH: begin
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// Note no state transition will occur if multdiv_hold is set
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md_state_d = MD_IDLE;
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multdiv_hold = ~multdiv_ready_id_i;
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end
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default: begin
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md_state_d = MD_IDLE;
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end
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endcase // md_state_q
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end // (mult_sel_i || div_sel_i)
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end
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//////////////////////////////////////////
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// Mutliplier / Divider state registers //
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//////////////////////////////////////////
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assign multdiv_en = (mult_en_i | div_en_i) & ~multdiv_hold;
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always_ff @(posedge clk_i or negedge rst_ni) begin
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if (!rst_ni) begin
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multdiv_count_q <= 5'h0;
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op_b_shift_q <= 33'h0;
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op_a_shift_q <= 33'h0;
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md_state_q <= MD_IDLE;
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div_by_zero_q <= 1'b0;
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end else if (multdiv_en) begin
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multdiv_count_q <= multdiv_count_d;
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op_b_shift_q <= op_b_shift_d;
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op_a_shift_q <= op_a_shift_d;
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md_state_q <= md_state_d;
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div_by_zero_q <= div_by_zero_d;
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end
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end
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/////////////
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// Outputs //
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/////////////
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assign valid_o = (md_state_q == MD_FINISH) |
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(md_state_q == MD_LAST &
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(operator_i == MD_OP_MULL |
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operator_i == MD_OP_MULH));
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assign multdiv_result_o = div_en_i ? accum_window_q[31:0] : res_adder_l[31:0];
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////////////////
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// Assertions //
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////////////////
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// State must be valid.
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`ASSERT(IbexMultDivStateValid, md_state_q inside {
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MD_IDLE, MD_ABS_A, MD_ABS_B, MD_COMP, MD_LAST, MD_CHANGE_SIGN, MD_FINISH
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}, clk_i, !rst_ni)
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`ifdef FORMAL
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`ifdef YOSYS
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`include "formal_tb_frag.svh"
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`endif
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`endif
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endmodule
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