mirror of
https://github.com/lowRISC/ibex.git
synced 2025-06-27 17:00:41 -04:00
187944c417
This commit includes switching to a scrambling RAM primitive for ICache data and tag RAMs. Also introduces minor changes to ICache to handle scrambling key valid signal. It also includes a minor bug fix regarding not initializing `fill_way_q` signal without ResetAll parameter. When the parameter is not set and we have our first hit right after ICache enables, the signal hangs. Signed-off-by: Canberk Topal <ctopal@lowrisc.org>
299 lines
9.3 KiB
Systemverilog
299 lines
9.3 KiB
Systemverilog
// Copyright lowRISC contributors.
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// Licensed under the Apache License, Version 2.0, see LICENSE for details.
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// SPDX-License-Identifier: Apache-2.0
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// VCS does not support overriding enum and string parameters via command line. Instead, a `define
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// is used that can be set from the command line. If no value has been specified, this gives a
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// default. Other simulators don't take the detour via `define and can override the corresponding
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// parameters directly.
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`ifndef RV32M
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`define RV32M ibex_pkg::RV32MFast
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`endif
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`ifndef RV32B
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`define RV32B ibex_pkg::RV32BNone
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`endif
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`ifndef RegFile
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`define RegFile ibex_pkg::RegFileFF
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`endif
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/**
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* Ibex simple system
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*
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* This is a basic system consisting of an ibex, a 1 MB sram for instruction/data
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* and a small memory mapped control module for outputting ASCII text and
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* controlling/halting the simulation from the software running on the ibex.
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*
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* It is designed to be used with verilator but should work with other
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* simulators, a small amount of work may be required to support the
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* simulator_ctrl module.
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*/
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module ibex_simple_system (
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input IO_CLK,
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input IO_RST_N
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);
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parameter bit SecureIbex = 1'b0;
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parameter bit ICacheScramble = 1'b0;
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parameter bit PMPEnable = 1'b0;
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parameter int unsigned PMPGranularity = 0;
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parameter int unsigned PMPNumRegions = 4;
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parameter bit RV32E = 1'b0;
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parameter ibex_pkg::rv32m_e RV32M = `RV32M;
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parameter ibex_pkg::rv32b_e RV32B = `RV32B;
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parameter ibex_pkg::regfile_e RegFile = `RegFile;
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parameter bit BranchTargetALU = 1'b0;
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parameter bit WritebackStage = 1'b0;
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parameter bit ICache = 1'b0;
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parameter bit ICacheECC = 1'b0;
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parameter bit BranchPredictor = 1'b0;
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parameter SRAMInitFile = "";
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logic clk_sys = 1'b0, rst_sys_n;
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typedef enum logic {
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CoreD
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} bus_host_e;
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typedef enum logic[1:0] {
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Ram,
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SimCtrl,
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Timer
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} bus_device_e;
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localparam int NrDevices = 3;
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localparam int NrHosts = 1;
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// interrupts
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logic timer_irq;
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// host and device signals
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logic host_req [NrHosts];
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logic host_gnt [NrHosts];
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logic [31:0] host_addr [NrHosts];
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logic host_we [NrHosts];
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logic [ 3:0] host_be [NrHosts];
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logic [31:0] host_wdata [NrHosts];
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logic host_rvalid [NrHosts];
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logic [31:0] host_rdata [NrHosts];
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logic host_err [NrHosts];
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// devices (slaves)
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logic device_req [NrDevices];
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logic [31:0] device_addr [NrDevices];
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logic device_we [NrDevices];
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logic [ 3:0] device_be [NrDevices];
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logic [31:0] device_wdata [NrDevices];
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logic device_rvalid [NrDevices];
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logic [31:0] device_rdata [NrDevices];
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logic device_err [NrDevices];
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// Device address mapping
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logic [31:0] cfg_device_addr_base [NrDevices];
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logic [31:0] cfg_device_addr_mask [NrDevices];
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assign cfg_device_addr_base[Ram] = 32'h100000;
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assign cfg_device_addr_mask[Ram] = ~32'hFFFFF; // 1 MB
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assign cfg_device_addr_base[SimCtrl] = 32'h20000;
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assign cfg_device_addr_mask[SimCtrl] = ~32'h3FF; // 1 kB
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assign cfg_device_addr_base[Timer] = 32'h30000;
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assign cfg_device_addr_mask[Timer] = ~32'h3FF; // 1 kB
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// Instruction fetch signals
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logic instr_req;
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logic instr_gnt;
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logic instr_rvalid;
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logic [31:0] instr_addr;
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logic [31:0] instr_rdata;
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logic instr_err;
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assign instr_gnt = instr_req;
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assign instr_err = '0;
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`ifdef VERILATOR
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assign clk_sys = IO_CLK;
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assign rst_sys_n = IO_RST_N;
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`else
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initial begin
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rst_sys_n = 1'b0;
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#8
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rst_sys_n = 1'b1;
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end
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always begin
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#1 clk_sys = 1'b0;
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#1 clk_sys = 1'b1;
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end
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`endif
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// Tie-off unused error signals
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assign device_err[Ram] = 1'b0;
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assign device_err[SimCtrl] = 1'b0;
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bus #(
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.NrDevices ( NrDevices ),
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.NrHosts ( NrHosts ),
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.DataWidth ( 32 ),
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.AddressWidth ( 32 )
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) u_bus (
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.clk_i (clk_sys),
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.rst_ni (rst_sys_n),
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.host_req_i (host_req ),
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.host_gnt_o (host_gnt ),
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.host_addr_i (host_addr ),
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.host_we_i (host_we ),
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.host_be_i (host_be ),
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.host_wdata_i (host_wdata ),
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.host_rvalid_o (host_rvalid ),
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.host_rdata_o (host_rdata ),
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.host_err_o (host_err ),
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.device_req_o (device_req ),
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.device_addr_o (device_addr ),
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.device_we_o (device_we ),
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.device_be_o (device_be ),
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.device_wdata_o (device_wdata ),
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.device_rvalid_i (device_rvalid),
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.device_rdata_i (device_rdata ),
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.device_err_i (device_err ),
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.cfg_device_addr_base,
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.cfg_device_addr_mask
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);
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ibex_top_tracing #(
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.SecureIbex ( SecureIbex ),
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.ICacheScramble ( ICacheScramble ),
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.PMPEnable ( PMPEnable ),
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.PMPGranularity ( PMPGranularity ),
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.PMPNumRegions ( PMPNumRegions ),
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.MHPMCounterNum ( 29 ),
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.RV32E ( RV32E ),
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.RV32M ( RV32M ),
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.RV32B ( RV32B ),
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.RegFile ( RegFile ),
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.BranchTargetALU ( BranchTargetALU ),
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.ICache ( ICache ),
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.ICacheECC ( ICacheECC ),
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.WritebackStage ( WritebackStage ),
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.BranchPredictor ( BranchPredictor ),
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.DmHaltAddr ( 32'h00100000 ),
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.DmExceptionAddr ( 32'h00100000 )
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) u_top (
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.clk_i (clk_sys),
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.rst_ni (rst_sys_n),
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.test_en_i ('b0),
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.scan_rst_ni (1'b1),
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.ram_cfg_i ('b0),
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.hart_id_i (32'b0),
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// First instruction executed is at 0x0 + 0x80
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.boot_addr_i (32'h00100000),
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.instr_req_o (instr_req),
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.instr_gnt_i (instr_gnt),
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.instr_rvalid_i (instr_rvalid),
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.instr_addr_o (instr_addr),
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.instr_rdata_i (instr_rdata),
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.instr_rdata_intg_i ('0),
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.instr_err_i (instr_err),
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.data_req_o (host_req[CoreD]),
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.data_gnt_i (host_gnt[CoreD]),
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.data_rvalid_i (host_rvalid[CoreD]),
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.data_we_o (host_we[CoreD]),
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.data_be_o (host_be[CoreD]),
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.data_addr_o (host_addr[CoreD]),
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.data_wdata_o (host_wdata[CoreD]),
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.data_wdata_intg_o (),
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.data_rdata_i (host_rdata[CoreD]),
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.data_rdata_intg_i ('0),
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.data_err_i (host_err[CoreD]),
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.irq_software_i (1'b0),
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.irq_timer_i (timer_irq),
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.irq_external_i (1'b0),
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.irq_fast_i (15'b0),
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.irq_nm_i (1'b0),
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.scramble_key_valid_i ('0),
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.scramble_key_i ('0),
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.scramble_nonce_i ('0),
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.scramble_req_o (),
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.debug_req_i ('b0),
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.crash_dump_o (),
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.fetch_enable_i ('b1),
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.alert_minor_o (),
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.alert_major_o (),
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.core_sleep_o ()
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);
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// SRAM block for instruction and data storage
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ram_2p #(
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.Depth(1024*1024/4),
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.MemInitFile(SRAMInitFile)
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) u_ram (
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.clk_i (clk_sys),
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.rst_ni (rst_sys_n),
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.a_req_i (device_req[Ram]),
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.a_we_i (device_we[Ram]),
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.a_be_i (device_be[Ram]),
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.a_addr_i (device_addr[Ram]),
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.a_wdata_i (device_wdata[Ram]),
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.a_rvalid_o (device_rvalid[Ram]),
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.a_rdata_o (device_rdata[Ram]),
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.b_req_i (instr_req),
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.b_we_i (1'b0),
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.b_be_i (4'b0),
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.b_addr_i (instr_addr),
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.b_wdata_i (32'b0),
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.b_rvalid_o (instr_rvalid),
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.b_rdata_o (instr_rdata)
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);
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simulator_ctrl #(
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.LogName("ibex_simple_system.log")
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) u_simulator_ctrl (
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.clk_i (clk_sys),
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.rst_ni (rst_sys_n),
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.req_i (device_req[SimCtrl]),
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.we_i (device_we[SimCtrl]),
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.be_i (device_be[SimCtrl]),
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.addr_i (device_addr[SimCtrl]),
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.wdata_i (device_wdata[SimCtrl]),
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.rvalid_o (device_rvalid[SimCtrl]),
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.rdata_o (device_rdata[SimCtrl])
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);
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timer #(
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.DataWidth (32),
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.AddressWidth (32)
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) u_timer (
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.clk_i (clk_sys),
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.rst_ni (rst_sys_n),
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.timer_req_i (device_req[Timer]),
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.timer_we_i (device_we[Timer]),
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.timer_be_i (device_be[Timer]),
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.timer_addr_i (device_addr[Timer]),
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.timer_wdata_i (device_wdata[Timer]),
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.timer_rvalid_o (device_rvalid[Timer]),
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.timer_rdata_o (device_rdata[Timer]),
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.timer_err_o (device_err[Timer]),
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.timer_intr_o (timer_irq)
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);
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export "DPI-C" function mhpmcounter_get;
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function automatic longint unsigned mhpmcounter_get(int index);
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return u_top.u_ibex_top.u_ibex_core.cs_registers_i.mhpmcounter[index];
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endfunction
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endmodule
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