Pirmin Vogel 2a42c23eaf [rtl] Decouple mip and mie CSRs ... This commit modifies the `mip` CSR to not depend on the `mie` CSR. While the values of both these CSRs are combined to decide whether an interrupt shall be handled, the RISC-V spec does not state that the content of of `mip` should depend on `mie`. This commit better aligns Ibex with other open-source RISC-V cores. This resolves lowRISC/ibex#567 reported by @pfmooney. Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>		2020-02-04 16:15:38 +01:00
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verilator_waiver.vlt	[rtl] Decouple mip and mie CSRs	2020-02-04 16:15:38 +01:00