ganoam 86979e603f [examples] Add Dual-Port Memory to Simple System ... This commit adds a separate memory ports for instruction and data fetches to the Simple System example. * Add Dual-Port RAM with 1 cycle read/write delay, 32 bit words. * Introduce parametric signal width definitions for bus implementation to work with a single host / device. * Modify Simple System top module to instantiate the new dual-port RAM.		2020-01-29 16:50:52 +01:00
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fpga/xilinx	Use shared code for Arty A7-100T example	2019-11-14 13:20:19 +01:00
sim	Add Synopsys VCS Support for Ibex Simple System	2019-12-03 16:41:26 +00:00
bus.sv	[examples] Add Dual-Port Memory to Simple System	2020-01-29 16:50:52 +01:00
prim_assert.sv	Include assert macros when they are used	2020-01-28 14:46:48 +00:00
prim_clock_gating.sv	[dv] Remove clock gating primitive in dv/uvm/tb	2019-11-16 00:25:32 +01:00
ram_1p.sv	Reverse return code of simutil_verilator_set_mem()	2019-11-28 18:45:11 +00:00
ram_2p.sv	[examples] Add Dual-Port Memory to Simple System	2020-01-29 16:50:52 +01:00
timer.sv	Include assert macros when they are used	2020-01-28 14:46:48 +00:00