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f2fccaadbc
- Fix incorrect address output to mepc on interrupt (fixes #320) - Fix instruction address changing before grant (fixes #296) - Suppress requests and reg writes on fetch error (fixes #340) - Remove excess address flops in fetch_fifo - Remove restriction on outstanding requests
51 lines
3.2 KiB
ReStructuredText
51 lines
3.2 KiB
ReStructuredText
.. _instruction-fetch:
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Instruction Fetch
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=================
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The Instruction-Fetch (IF) stage of the core is able to supply one instruction to the Instruction-Decode (ID) stage per cycle if the instruction cache or the instruction memory is able to serve one instruction per cycle.
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For optimal performance and timing closure reasons, a prefetcher is used which fetches instructions from the instruction memory, or instruction cache.
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The following table describes the signals that are used to fetch instructions.
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This interface is a simplified version of the interface used on the data interface as described in :ref:`load-store-unit`.
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The main difference is that the instruction interface does not allow for write transactions and thus needs less signals.
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.. tabularcolumns:: |p{4cm}|l|p{9cm}|
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+-------------------------+-----------+-----------------------------------------------+
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| Signal | Direction | Description |
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+=========================+===========+===============================================+
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| ``instr_req_o`` | output | Request valid, must stay high until |
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| | | ``instr_gnt_i`` is high for one cycle |
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+-------------------------+-----------+-----------------------------------------------+
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| ``instr_addr_o[31:0]`` | output | Address, word aligned |
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+-------------------------+-----------+-----------------------------------------------+
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| ``instr_gnt_i`` | input | The other side accepted the request. |
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| | | ``instr_req_o`` may be deasserted in the next |
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| | | cycle. |
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+-------------------------+-----------+-----------------------------------------------+
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| ``instr_rvalid_i`` | input | ``instr_rdata_i`` holds valid data when |
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| | | ``instr_rvalid_i`` is high. This signal will |
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| | | be high for exactly one cycle per request. |
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+-------------------------+-----------+-----------------------------------------------+
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| ``instr_rdata_i[31:0]`` | input | Data read from memory |
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+-------------------------+-----------+-----------------------------------------------+
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| ``instr_err_i`` | input | Memory access error |
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+-------------------------+-----------+-----------------------------------------------+
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Misaligned Accesses
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-------------------
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Externally, the IF interface performs word-aligned instruction fetches only.
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Misaligned instruction fetches are handled by performing two separate word-aligned instruction fetches.
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Internally, the core can deal with both word- and half-word-aligned instruction addresses to support compressed instructions.
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The LSB of the instruction address is ignored internally.
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Protocol
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--------
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The protocol used to communicate with the instruction cache or the instruction memory is very similar to the protocol used by the LSU on the data interface of Ibex.
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See the description of the LSU in :ref:`LSU Protocol<lsu-protocol>` for details about this protocol.
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