Tobias Wölfel 76f6a3d4c3 Use shared code for Arty A7-100T example ... Move Xilinx specific code into shared folder so it can be re-used by different examples. Use the shared RAM code and make use of byte enable signal. Fixes lowrisc/ibex#144		2019-11-14 13:20:19 +01:00
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fpga/xilinx	Use shared code for Arty A7-100T example	2019-11-14 13:20:19 +01:00
sim	Delay simulator finish	2019-11-14 11:57:12 +00:00
bus.sv	Added top-level shared directory	2019-11-09 07:48:47 +00:00
prim_clock_gating.sv	Added top-level shared directory	2019-11-09 07:48:47 +00:00
ram_1p.sv	Added top-level shared directory	2019-11-09 07:48:47 +00:00