udinator 6ce8b6ecf2 Update google_riscv-dv to google/riscv-dv@4b333ba (#462) ... Update code from upstream repository https://github.com/google/riscv- dv to revision 4b333ba1ef285ec4508c606efa64610136154a5e * cg instantion based on supported_isa (google/riscv-dv#303) (udinator) * Fix coverage collection issue, change default target to rv32imc (google/riscv-dv#302) (taoliug) * Integrate whisper(swerv-ISS) (google/riscv-dv#301) (taoliug) * Fix cov.py, set UVM_VERBOSITY to UVM_HIGH for verbose mode (google/riscv-dv#299) (taoliug) * Fix jalr handling issue for ovpsim (google/riscv-dv#298) (taoliug) * Add noclean option, change default output directory of coverage collection (google/riscv-dv#297) (taoliug) * Enable using core trace logs for coverage collection (google/riscv- dv#291) (udinator) * Fix isa/mabi setup issue for RV64GC target (google/riscv-dv#296) (taoliug) * fixed line widths (x2) and check error returns for any questa simalator (google/riscv-dv#293) (simond-imperas) * Unknown instruction fix (google/riscv-dv#290) (simond-imperas) * Fix ovpsim log process issue (google/riscv-dv#289) (udinator) * adding riscvOVPsim vector instruction trace to csv processing - start (3rd Attempt) (google/riscv-dv#288) (simond-imperas) Signed-off-by: Udi <udij@google.com>		2019-11-12 14:39:22 -08:00
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google_riscv-dv	Update google_riscv-dv to google/riscv-dv@4b333ba (#462)	2019-11-12 14:39:22 -08:00
google_riscv-dv.lock.hjson	Update google_riscv-dv to google/riscv-dv@4b333ba (#462)	2019-11-12 14:39:22 -08:00
google_riscv-dv.vendor.hjson	Integrate riscv-dv upstream changes (#107)	2019-07-01 08:59:31 -07:00