ganoam 48c4b6a5ea [rtl] Add Single Cycle Multiplier targeting FPGA ... * Integrate option to implement a multiplier using 3 parallel 17 bit multipliers in order to compute MUL instructions in 1 cycle MULH in 2 cycles. * Add parameter SingleCycleMultiply to select single cycle multiplication. The single cycle multiplication capability is intended for FPGA targets. Using three parallel multiplication units improves performance of multiplication operations at the cost of DSP primitives. For ASIC targets, the area consumed by the multiplication structure will grow approximately 3-4x. The functionality is selected within the module using the parameter `SingleCycleMultiply`. From the top level it can be chosen by setting the parameter `MultiplierImplementation` to 'single_cc'. Signed-off-by: ganoam <gnoam@live.com>		2020-02-11 16:09:41 +01:00
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verilator_waiver.vlt	[rtl] Add Single Cycle Multiplier targeting FPGA	2020-02-11 16:09:41 +01:00