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Update code from upstream repository https://github.com/google/riscv- dv to revision 6cf6b4f389272d8ff5e2b397af43ac6c0dfba2e2 * Update init value for floating point reg (google/riscv-dv#615) (weicaiyang) * temporarily comment out 4 vector instructions to re-enable coverage flow (google/riscv-dv#616) (udinator) * Fix vector load/store instruction encoding (google/riscv-dv#614) (taoliug) * Add user_init.s to allow custom initialization routine (google/riscv-dv#613) (taoliug) * Fix vector extension config register initialization (google/riscv- dv#610) (taoliug) * Add floating point coverage part2 (google/riscv-dv#600) (weicaiyang) * Add MAX LMUL configure (google/riscv-dv#609) (taoliug) * Fix vector unit strided load/store instruction stream name (google/riscv-dv#608) (taoliug) * Update pygen source files (google/riscv-dv#602) (ANIL SHARMA) * Add vector strided load/store test (google/riscv-dv#601) (taoliug) * make <main> 4-byte aligned when enabling PMP (google/riscv-dv#596) (udinator) * Fix ius compilation issue (google/riscv-dv#599) (taoliug) * Integrate Andes's vector extension work to upstream (google/riscv- dv#598) (taoliug) * Fix kernal setcion PTE setting issue (google/riscv-dv#594) (taoliug) * Add flake8 check for pygen (google/riscv-dv#589) (Hai Hoang Dang) * Fix MPRV setting issue, it's causing problem for exception handling with virtual address translation on (google/riscv-dv#593) (taoliug) * Fix VSETVL generation issue (google/riscv-dv#591) (taoliug) * Fix jump instruction stream label issue (google/riscv-dv#590) (taoliug) * Add pygen_src files (aneels3) Signed-off-by: Udi <udij@google.com> |
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eembc_coremark | ||
google_riscv-dv | ||
lowrisc_ip | ||
patches/eembc_coremark | ||
eembc_coremark.lock.hjson | ||
google_riscv-dv.lock.hjson | ||
google_riscv-dv.vendor.hjson | ||
lowrisc_ip.lock.hjson | ||
lowrisc_ip.vendor.hjson |