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af8343d366
Change encoding of hardware loop setup instructions, displacement by one bit and unsigned
516 lines
16 KiB
Systemverilog
516 lines
16 KiB
Systemverilog
////////////////////////////////////////////////////////////////////////////////
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// Company: IIS @ ETHZ - Federal Institute of Technology //
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// DEI @ UNIBO - University of Bologna //
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// //
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// Engineer: Andreas Traber - atraber@iis.ee.ethz.ch //
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// //
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// Additional contributions by: //
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// //
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// //
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// Create Date: 06/08/2014 //
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// Design Name: RISC-V processor core //
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// Module Name: prefetch_buffer.sv //
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// Project Name: RI5CY //
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// Language: SystemVerilog //
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// //
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// Description: Prefetch Buffer that caches instructions. This cuts overly //
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// long critical paths to the instruction cache //
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// //
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// Revision: //
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// Revision v0.1 - File Created //
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// //
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// //
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// //
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////////////////////////////////////////////////////////////////////////////////
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// input port: send address one cycle before the data
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// clear_i clears the FIFO for the following cycle. in_addr_i can be sent in
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// this cycle already
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module riscv_fetch_fifo
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(
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input logic clk,
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input logic rst_n,
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// control signals
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input logic branch_i, // clears the contents of the fifo
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input logic hwloop_i, // tries to insert an entry above the first one
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// input port
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input logic in_addr_valid_i,
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output logic in_addr_ready_o,
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input logic [31:0] in_addr_i,
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output logic [31:0] in_last_addr_o,
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input logic in_rdata_valid_i,
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output logic in_rdata_ready_o,
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input logic [31:0] in_rdata_i,
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// output port
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output logic out_valid_o,
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input logic out_ready_i,
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output logic [31:0] out_rdata_o,
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output logic [31:0] out_addr_o,
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output logic out_is_hwlp_o
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);
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localparam DEPTH = 3; // must be 2 or greater
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// index 0 is used for output
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logic [0:DEPTH-1] [31:0] addr_n, addr_int, addr_Q;
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logic [0:DEPTH-1] addr_valid_n, addr_valid_int, addr_valid_Q;
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logic [0:DEPTH-1] [31:0] rdata_n, rdata_int, rdata_Q;
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logic [0:DEPTH-1] rdata_valid_n, rdata_valid_int, rdata_valid_Q;
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logic [0:1 ] is_hwlp_n, is_hwlp_int, is_hwlp_Q;
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logic [31:0] rdata, rdata_unaligned;
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logic valid, valid_unaligned;
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logic aligned_is_compressed, unaligned_is_compressed;
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logic hwlp_inbound;
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//////////////////////////////////////////////////////////////////////////////
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// output port
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//////////////////////////////////////////////////////////////////////////////
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assign rdata = (rdata_valid_Q[0]) ? rdata_Q[0] : in_rdata_i;
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assign valid = (rdata_valid_Q[0] || (addr_valid_Q[0] && in_rdata_valid_i));
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assign rdata_unaligned = (rdata_valid_Q[1]) ? {rdata_Q[1][15:0], rdata[31:16]} : {in_rdata_i[15:0], rdata[31:16]};
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// it is implied that rdata_valid_Q[0] is set
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assign valid_unaligned = (rdata_valid_Q[1] || (addr_valid_Q[1] && in_rdata_valid_i));
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assign unaligned_is_compressed = rdata[17:16] != 2'b11;
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assign aligned_is_compressed = rdata[1:0] != 2'b11;
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//////////////////////////////////////////////////////////////////////////////
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// instruction aligner (if unaligned)
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//////////////////////////////////////////////////////////////////////////////
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always_comb
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begin
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// serve the aligned case even though the output address is unaligned when
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// the next instruction will be from a hardware loop target
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// in this case the current instruction is already prealigned in element 0
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if (out_addr_o[1] && (~is_hwlp_Q[1])) begin
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// unaligned case
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out_rdata_o = rdata_unaligned;
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if (unaligned_is_compressed)
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out_valid_o = 1'b1;
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else
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out_valid_o = valid_unaligned;
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end else begin
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// aligned case
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out_rdata_o = rdata;
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out_valid_o = valid;
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end
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end
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assign out_addr_o = addr_Q[0]; // always output addr directly since we sent it one cycle earlier to the FIFO
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assign out_is_hwlp_o = is_hwlp_Q[0];
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//////////////////////////////////////////////////////////////////////////////
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// input port
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//////////////////////////////////////////////////////////////////////////////
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// we accept addresses as long as our fifo is not full or we are cleared
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assign in_addr_ready_o = branch_i || (~addr_valid_Q[DEPTH-1]);
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// we accept data as long as our fifo is not full
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// we don't care about clear here as the data will be received one cycle
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// later anyway
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assign in_rdata_ready_o = ~rdata_valid_Q[DEPTH-1];
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// output the latest valid address we got
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int i;
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always_comb
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begin
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in_last_addr_o = addr_Q[0];
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for(i = 1; i < DEPTH; i++) begin
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if (addr_valid_Q[i])
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in_last_addr_o = addr_Q[i];
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end
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end
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// accept hwloop input as long as our second entry is not already one
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assign hwlp_inbound = hwloop_i & (~is_hwlp_Q[1]);
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//////////////////////////////////////////////////////////////////////////////
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// FIFO management
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//////////////////////////////////////////////////////////////////////////////
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int j;
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always_comb
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begin
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addr_int = addr_Q;
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addr_valid_int = addr_valid_Q;
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is_hwlp_int = is_hwlp_Q;
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if (in_addr_valid_i && in_addr_ready_o) begin
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for(j = 0; j < DEPTH; j++) begin
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if (~addr_valid_Q[j]) begin
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addr_int[j] = in_addr_i;
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addr_valid_int[j] = 1'b1;
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break;
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end
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end
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end
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// on a hardware loop invalidate everything starting from the second entry
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if (hwlp_inbound) begin
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addr_int[1] = in_addr_i;
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addr_valid_int[1] = 1'b1;
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addr_valid_int[2:DEPTH-1] = '0;
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is_hwlp_int[1] = 1'b1;
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end
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end
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int k;
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always_comb
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begin
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rdata_int = rdata_Q;
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rdata_valid_int = rdata_valid_Q;
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if (in_rdata_valid_i && in_rdata_ready_o) begin
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for(k = 0; k < DEPTH; k++) begin
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if (~rdata_valid_Q[k]) begin
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rdata_int[k] = in_rdata_i;
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rdata_valid_int[k] = 1'b1;
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break;
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end
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end
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end
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// on a hardware loop invalidate everything starting from the second entry
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if (hwlp_inbound) begin
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rdata_int[0] = out_rdata_o; // save current output in rdata_int[0], so that we have it available even though we override entry #1
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rdata_valid_int[1:DEPTH-1] = '0;
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end
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end
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// move everything by one step
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always_comb
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begin
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addr_n = addr_int;
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addr_valid_n = addr_valid_int;
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rdata_n = rdata_int;
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rdata_valid_n = rdata_valid_int;
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is_hwlp_n = is_hwlp_int;
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if (out_ready_i && out_valid_o) begin
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// now take care of the addresses
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if (is_hwlp_int[1]) begin
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// hardware loop found in second entry
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addr_n = {addr_int[1][31:0], addr_int[2:DEPTH-1], 32'b0};
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addr_valid_n = {addr_valid_int[1:DEPTH-1], 1'b0};
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rdata_n = {rdata_int[1:DEPTH-1], 32'b0};
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rdata_valid_n = {rdata_valid_int[1:DEPTH-1], 1'b0};
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is_hwlp_n = {is_hwlp_int[1], 1'b0};
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end else begin
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if (addr_Q[0][1]) begin
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// unaligned case
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if (unaligned_is_compressed) begin
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addr_n = {{addr_int[1][31:2], 2'b00}, addr_int[2:DEPTH-1], 32'b0};
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end else begin
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addr_n = {{addr_int[1][31:2], 2'b10}, addr_int[2:DEPTH-1], 32'b0};
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end
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addr_valid_n = {addr_valid_int[1:DEPTH-1], 1'b0};
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rdata_n = {rdata_int[1:DEPTH-1], 32'b0};
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rdata_valid_n = {rdata_valid_int[1:DEPTH-1], 1'b0};
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is_hwlp_n = {is_hwlp_int[1], 1'b0};
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end else begin
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// aligned case
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if (aligned_is_compressed) begin
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// just increase address, do not move to next entry in FIFO
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addr_n[0] = {addr_int[0][31:2], 2'b10};
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is_hwlp_n[0] = 1'b0; // invalidate hwlp bit for current address
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end else begin
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// move to next entry in FIFO
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addr_n = {{addr_int[1][31:2], 2'b00}, addr_int[2:DEPTH-1], 32'b0};
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addr_valid_n = {addr_valid_int[1:DEPTH-1], 1'b0};
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rdata_n = {rdata_int[1:DEPTH-1], 32'b0};
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rdata_valid_n = {rdata_valid_int[1:DEPTH-1], 1'b0};
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is_hwlp_n = {is_hwlp_int[1], 1'b0};
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end
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end
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end
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end
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end
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//////////////////////////////////////////////////////////////////////////////
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// registers
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//////////////////////////////////////////////////////////////////////////////
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always_ff @(posedge clk, negedge rst_n)
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begin
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if(rst_n == 1'b0)
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begin
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addr_Q <= '{default: '0};
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addr_valid_Q <= '0;
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rdata_Q <= '{default: '0};
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rdata_valid_Q <= '0;
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is_hwlp_Q <= '0;
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end
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else
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begin
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// on a clear signal from outside we invalidate the content of the FIFO
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// completely and start from an empty state
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if (branch_i) begin
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addr_Q[0] <= in_addr_i;
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addr_valid_Q <= {in_addr_valid_i, {DEPTH-1{1'b0}}};
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rdata_valid_Q <= '0;
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is_hwlp_Q <= '0;
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end else begin
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addr_Q <= addr_n;
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addr_valid_Q <= addr_valid_n;
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rdata_Q <= rdata_n;
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rdata_valid_Q <= rdata_valid_n;
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is_hwlp_Q <= is_hwlp_n;
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end
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end
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end
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endmodule
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// branch_i deletes everything up to now, i.e. it assumes that addr_i now has
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// the correct state and uses the current cycle's addr_i to fetch new data
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module riscv_prefetch_buffer
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(
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input logic clk,
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input logic rst_n,
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input logic req_i,
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input logic branch_i,
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input logic [31:0] addr_i,
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input logic hwloop_i,
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input logic [31:0] hwloop_target_i,
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input logic ready_i,
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output logic valid_o,
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output logic [31:0] rdata_o,
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output logic [31:0] addr_o,
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output logic is_hwlp_o, // is set when the currently served data is from a hwloop
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// goes to instruction memory / instruction cache
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output logic instr_req_o,
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output logic [31:0] instr_addr_o,
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input logic instr_gnt_i,
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input logic instr_rvalid_i,
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input logic [31:0] instr_rdata_i,
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// Prefetch Buffer Status
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output logic busy_o
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);
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enum logic [1:0] {IDLE, WAIT_GNT, WAIT_RVALID, WAIT_ABORTED } CS, NS;
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logic [31:0] addr_next;
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logic fifo_addr_valid;
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logic fifo_addr_ready;
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logic [31:0] fifo_last_addr;
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logic fifo_rdata_valid;
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logic fifo_rdata_ready;
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//////////////////////////////////////////////////////////////////////////////
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// prefetch buffer status
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//////////////////////////////////////////////////////////////////////////////
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assign busy_o = (CS != IDLE) || instr_req_o;
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//////////////////////////////////////////////////////////////////////////////
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// address selection and increase
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//////////////////////////////////////////////////////////////////////////////
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always_comb
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begin
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addr_next = {fifo_last_addr[31:2], 2'b00} + 32'd4;
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if (branch_i) begin
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addr_next = addr_i;
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end else begin
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if (hwloop_i)
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addr_next = hwloop_target_i;
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end
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end
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//////////////////////////////////////////////////////////////////////////////
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// fetch fifo
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// consumes addresses and rdata
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//////////////////////////////////////////////////////////////////////////////
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riscv_fetch_fifo fifo_i
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(
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.clk ( clk ),
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.rst_n ( rst_n ),
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.branch_i ( branch_i ),
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.hwloop_i ( hwloop_i ),
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.in_addr_valid_i ( fifo_addr_valid ),
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.in_addr_ready_o ( fifo_addr_ready ),
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.in_addr_i ( addr_next ),
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.in_last_addr_o ( fifo_last_addr ),
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.in_rdata_valid_i ( fifo_rdata_valid ),
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.in_rdata_ready_o ( fifo_rdata_ready ),
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.in_rdata_i ( instr_rdata_i ),
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.out_valid_o ( valid_o ),
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.out_ready_i ( ready_i ),
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.out_rdata_o ( rdata_o ),
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.out_addr_o ( addr_o ),
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.out_is_hwlp_o ( is_hwlp_o )
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);
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//////////////////////////////////////////////////////////////////////////////
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// instruction fetch FSM
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// deals with instruction memory / instruction cache
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//////////////////////////////////////////////////////////////////////////////
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always_comb
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begin
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instr_req_o = 1'b0;
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instr_addr_o = addr_next;
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fifo_addr_valid = 1'b0;
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fifo_rdata_valid = 1'b0;
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NS = CS;
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unique case(CS)
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// default state, not waiting for requested data
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IDLE:
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begin
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instr_req_o = 1'b0;
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if ((req_i && fifo_addr_ready) || branch_i) begin
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instr_req_o = 1'b1;
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fifo_addr_valid = 1'b1;
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if(instr_gnt_i) //~> granted request
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NS = WAIT_RVALID;
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else begin //~> got a request but no grant
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NS = WAIT_GNT;
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end
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end
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end // case: IDLE
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// we sent a request but did not yet get a grant
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WAIT_GNT:
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begin
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instr_req_o = 1'b1;
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if (branch_i) begin
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instr_addr_o = addr_next;
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fifo_addr_valid = 1'b1;
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end else begin
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instr_addr_o = fifo_last_addr;
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end
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if(instr_gnt_i)
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NS = WAIT_RVALID;
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else
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NS = WAIT_GNT;
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end // case: WAIT_GNT
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// we wait for rvalid, after that we are ready to serve a new request
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WAIT_RVALID: begin
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if ((req_i && fifo_addr_ready) || branch_i) begin
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// prepare for next request
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instr_req_o = 1'b1;
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if (instr_rvalid_i) begin
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fifo_rdata_valid = 1'b1;
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fifo_addr_valid = 1'b1;
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if (instr_gnt_i) begin
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NS = WAIT_RVALID;
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end else begin
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NS = WAIT_GNT;
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end
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end else begin
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// we are requested to abort our current request
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// we didn't get an rvalid yet, so wait for it
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if (branch_i) begin
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fifo_addr_valid = 1'b1;
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NS = WAIT_ABORTED;
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end
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end
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end else begin
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// just wait for rvalid and go back to IDLE, no new request
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// requested
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instr_req_o = 1'b0;
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if (instr_rvalid_i) begin
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fifo_rdata_valid = 1'b1;
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NS = IDLE;
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end
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end
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end // case: WAIT_RVALID
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// our last request was aborted, but we didn't yet get a rvalid and
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// there was no new request sent yet
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// we assume that req_i is set to high
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WAIT_ABORTED: begin
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// prepare for next request
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instr_req_o = 1'b1;
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instr_addr_o = fifo_last_addr;
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if (instr_rvalid_i) begin
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// no need to send address, already done in WAIT_RVALID
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if (instr_gnt_i) begin
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NS = WAIT_RVALID;
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end else begin
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NS = WAIT_GNT;
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end
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end
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end
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default:
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begin
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NS = IDLE;
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instr_req_o = 1'b0;
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end
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endcase
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end
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//////////////////////////////////////////////////////////////////////////////
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// registers
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//////////////////////////////////////////////////////////////////////////////
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always_ff @(posedge clk, negedge rst_n)
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begin
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if(rst_n == 1'b0)
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begin
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CS <= IDLE;
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end
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else
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begin
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CS <= NS;
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end
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end
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endmodule
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