Philipp Wagner 1c82c20132 Remove property from assert message ... Assert macros in prim_assert.sv report the asserted property as part of the error message if the assertion fails. Doing that requires us to stringify the property. If the property is multi-line in the source code, this produces a multi-line string. According to the SystemVerilog standard, a multi-line string requires a backslash (`\`) at the end of a line. Adding this backslash through a macro is not possible (at least to my knowledge), giving us no way to produce a standards-compliant implementation of the `ASSERT` macros that report the property as string. This commit therefore removes the property from the error message if an assertion fails. It makes these messages less useful, but the information can still be recovered in a less convenient way through the name of the assertion, and the file and line numbers. File and line number were missing from the non-UVM code path before, this commit adds them there as well. Fixes #669		2020-03-13 10:47:40 +00:00
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rtl	Remove property from assert message	2020-03-13 10:47:40 +00:00
fpga_xilinx.core	Use shared code for Arty A7-100T example	2019-11-14 13:20:19 +01:00
prim_assert.core	Include assert macros when they are used	2020-01-28 14:46:48 +00:00
sim_shared.core	[examples] Add Dual-Port Memory to Simple System	2020-01-29 16:50:52 +01:00