Tom Roberts c054a63c3d [rtl] Instantiate instruction cache ... - Add parameters and actual instantiation of icache - Add a custom CSR in the M-mode custom RW range to enable the cache - Wire up the cache invalidation signal to trigger on fence.i Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>		2020-03-23 12:57:31 +00:00
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fpga/artya7	Merge pull request #624 from ganoam/fpga-opt-perf-mon-pr	2020-03-06 12:49:51 +01:00
simple_system	[rtl] Instantiate instruction cache	2020-03-23 12:57:31 +00:00
sw	[rtl/sw] Add multiply and divide wait counters	2020-03-13 14:48:29 +00:00