Udi 216ba1a42d Update google_riscv-dv to google/riscv-dv@3cf691d ... Update code from upstream repository https://github.com/google/riscv- dv to revision 3cf691dcb96f2cd72250690216b60f2b0c0ac804 * remove hardcoded CSR names (Udi Jonnalagadda) * initial custom CSR support (Udi Jonnalagadda) * Add support for segmented load/store instructions (google/riscv- dv#656) (taoliug) * fix post_randomize issue (aneels3) * add MAX_LMUL to rv32i config (google/riscv-dv#649) (udinator) * Ignore log and asm file (aneels3) * Add Command Line Support (aneels3) * support for command-line arguments (pvipsyash) * Reorder import statements (aneels3) * Modified function randomize_gpr in instr_stream file (ShraddhaDevaiya) * Updated riscv_instr_sequence file and modified other python files to get main block in asm file. (ShraddhaDevaiya) * Modify get_rand_instr() (aneels3) * added uvm_glob_to_re in uvm_re_match (Dawid Zimonczyk) * Aldec Riviera-PRO compiler command line arguments modified. (google/riscv-dv#638) (Dariusz Stachańczyk) * allow coverage compilation to be run on LSF (google/riscv-dv#637) (udinator) * Add CHIPS Alliance work group information to the README (google/riscv-dv#633) (taoliug) * Add indexed/strided vector load/store instrution stream (google/riscv-dv#632) (taoliug) * Add constraint for mtvec alignment in vectored interrupt mode (google/riscv-dv#631) (taoliug) * Add bitstring requirement to pygen/experimental README (google/riscv-dv#630) (taoliug) * Add unsupported load/store instruction filtering (google/riscv- dv#629) (taoliug) * Add different methods to initialize the vregs (google/riscv-dv#627) (Josep Sans) * Support a vetor instruction only mode (google/riscv-dv#626) (taoliug) * Add riscv_instr_stream.py file (aneels3) * Importing PyVSC module (google/riscv-dv#625) (Hodjat Asghari Esfeden) * update pygen_src files (google/riscv-dv#612) (BharathNR1030) * Fix typo (google/riscv-dv#624) (taoliug) * Fix B-ext instruction generation issue (google/riscv-dv#620) (taoliug) Signed-off-by: Udi <udij@google.com>		2020-07-24 00:09:07 -07:00
..
eembc_coremark	Update eembc_coremark to eembc/coremark@0c91314	2020-03-09 14:41:40 +00:00
google_riscv-dv	Update google_riscv-dv to google/riscv-dv@3cf691d	2020-07-24 00:09:07 -07:00
lowrisc_ip	Properly vendor in mem_model from OpenTitan	2020-07-24 08:05:40 +01:00
patches	Define an Ibex-specific top_pkg core	2020-07-22 21:09:25 +01:00
eembc_coremark.lock.hjson	Update eembc_coremark to eembc/coremark@0c91314	2020-03-09 14:41:40 +00:00
google_riscv-dv.lock.hjson	Update google_riscv-dv to google/riscv-dv@3cf691d	2020-07-24 00:09:07 -07:00
google_riscv-dv.vendor.hjson	exclude tar.gz compressed file from vendoring, and remove from vendor directory (#550)	2020-01-09 15:50:34 -08:00
lowrisc_ip.lock.hjson	Update lowrisc_ip to lowRISC/opentitan@067272a2	2020-07-24 08:05:40 +01:00
lowrisc_ip.vendor.hjson	Properly vendor in mem_model from OpenTitan	2020-07-24 08:05:40 +01:00