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e5bb1447cc
completely generic The only dependency that limits the number of hwloops now is the encoding, the rest adapts automatically
84 lines
3.3 KiB
Systemverilog
84 lines
3.3 KiB
Systemverilog
////////////////////////////////////////////////////////////////////////////////
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// Company: IIS @ ETHZ - Federal Institute of Technology //
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// DEI @ UNIBO - University of Bologna //
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// //
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// Engineer: Michael Gautschi - gautschi@iis.ee.ethz.ch //
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// //
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// Additional contributions by: //
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// //
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// //
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// Create Date: 08/08/2014 //
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// Design Name: hwloop controller //
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// Module Name: hwloop_controller.sv //
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// Project Name: RI5CY //
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// Language: SystemVerilog //
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// //
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// Description: Hardware loop controller unit. This unit is responsible to //
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// handle hardware loops. Tasks are: //
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// a) compare PC to all stored end addresses //
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// b) jump to the right start address if counter =/ 0 //
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// //
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// Revision: //
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// Revision v0.1 - File Created //
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// //
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// //
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// //
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////////////////////////////////////////////////////////////////////////////////
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`include "defines.sv"
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module riscv_hwloop_controller
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#(
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parameter N_REGS = 2
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)
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(
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// from id stage
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input logic [31:0] current_pc_i,
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// from hwloop_regs
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input logic [N_REGS-1:0] [31:0] hwlp_start_addr_i,
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input logic [N_REGS-1:0] [31:0] hwlp_end_addr_i,
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input logic [N_REGS-1:0] [31:0] hwlp_counter_i,
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// to hwloop_regs
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output logic [N_REGS-1:0] hwlp_dec_cnt_o,
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// to id stage
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output logic hwlp_jump_o,
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output logic [31:0] hwlp_targ_addr_o
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);
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logic [N_REGS-1:0] pc_is_end_addr;
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// end address detection
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integer j;
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// generate comparators. check for end address and the loop counter
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genvar i;
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for (i = 0; i < N_REGS; i++) begin
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assign pc_is_end_addr[i] = (current_pc_i == hwlp_end_addr_i[i]) &&
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(hwlp_counter_i[i] > 32'h1);
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end
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// output signal for ID stage
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assign hwlp_jump_o = (|pc_is_end_addr);
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// select corresponding start address and decrement counter
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always_comb
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begin
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hwlp_targ_addr_o = 'x;
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hwlp_dec_cnt_o = '0;
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for (j = N_REGS-1; j >= 0; j--) begin
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if (pc_is_end_addr[j]) begin
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hwlp_targ_addr_o = hwlp_start_addr_i[j];
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hwlp_dec_cnt_o[j] = 1'b1;
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end
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end
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end
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endmodule
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