Tobias Wölfel ce7e38351e [DV] Add Verilator memory initialization from ELF ... Support initialization of memory by loading content from ELF files. All segments of the ELF file with the type `PT_LOAD` are merged into a temporary buffer and then forwarded to a predefined memory. This is an addition for setting the memories with VMEM files. Memories must implement `simutil_verilator_set_mem` to support the setting of values with a width of 32 bits. A return value of 0 must indicate a successful operation and 1 an error. Memories are defined by a call to `RegisterMemoryArea()` before the execution of the simulation, at which point the arguments are parsed and the initialization is started. The memories are identified by unique name. The design specific location is used to set the SystemVerilog scope. Registered memories can be printed by using `-l list`. The unique name is used for `-l name,file.elf` together with the file path. An optional part of the argument is the type of the file, `elf` or `vmem`, and if not provided it is attempted to detect the type by looking at the file extension. The memory specific arguments which already existed accept now also ELF files. They use predefined names and are included to keep the interface stable. Contents of an ELF segment which has a bigger memory size than file size are not set. This is typically required for BSS sections for zero-ing the memory.		2019-11-27 11:35:07 +00:00
..
fpga/artya7-100	Update fusesoc usage	2019-11-14 13:20:19 +01:00
simple_system	[DV] Add Verilator memory initialization from ELF	2019-11-27 11:35:07 +00:00
sw	Use shared code for Arty A7-100T example	2019-11-14 13:20:19 +01:00