Pirmin Vogel 40d6368983 [dv] Remove clock gating primitive in dv/uvm/tb ... This commit removes a copy of the dummy clock gating primitive from tree previously used for UVM-based DV. There is another, identical copy of the same primitive in `shared/rtl` that can be used instead. This resolves lowRISC/ibex#213. Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>		2019-11-16 00:25:32 +01:00
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rtl	[dv] Remove clock gating primitive in dv/uvm/tb	2019-11-16 00:25:32 +01:00
fpga_xilinx.core	Use shared code for Arty A7-100T example	2019-11-14 13:20:19 +01:00
sim_shared.core	Added simple system	2019-11-09 07:48:47 +00:00