Pirmin Vogel ac51db259d Set FPGA_XILINX define whenever Vivado is used ... This commit makes sure that whenever Vivado is used, the Verilog define `FPGA_XILINX` is set. This define can be used to enable Xilinx specific pragmas in the RTL code. It is currently used to implement the performance counters with DSP slices (incl. integrated output registers for counter widths <= 32) which helps to save logic resources and FFs (-7% and -15% when using e.g. 10 counters). Previously, we had to set this parameter in every single top-level .core file using Ibex. Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>		2020-08-04 12:36:27 +02:00
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fpga/artya7	Set FPGA_XILINX define whenever Vivado is used	2020-08-04 12:36:27 +02:00
simple_system	[rtl] Add alert outputs	2020-07-15 09:50:23 +01:00
sw	Fix typo in examples/sw/benchmarks/README.md	2020-07-30 16:34:03 +01:00