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ibex/shared
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Tom Roberts d5ee96fff6 [rtl] Add dummy instruction insertion 
- Adds a new module in the IF stage to inject dummy instructions into
  the pipeline
- Control / frequency of insertion is governed by configuration CSRs
- Extra CSR added to allow reseed of the internal LFSR useed for
  randomizing insertion
- Extra logic added to the register file to make dummy instruction
  writebacks look like real intructions (via the zero register)

Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
2020-05-21 13:58:01 +01:00
..
rtl [rtl] Add dummy instruction insertion 2020-05-21 13:58:01 +01:00
fpga_xilinx.core Use shared code for Arty A7-100T example 2019-11-14 13:20:19 +01:00
prim_assert.core Include assert macros when they are used 2020-01-28 14:46:48 +00:00
prim_generic_ram_1p.core [prim] Split out primitives used by icache 2020-05-04 17:19:58 +01:00
prim_lfsr.core [rtl] Add dummy instruction insertion 2020-05-21 13:58:01 +01:00
prim_ram_1p.core [prim] Split out primitives used by icache 2020-05-04 17:19:58 +01:00
prim_secded.core [prim] Split out primitives used by icache 2020-05-04 17:19:58 +01:00
sim_shared.core [prim] Split out primitives used by icache 2020-05-04 17:19:58 +01:00