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167 lines
12 KiB
ReStructuredText
167 lines
12 KiB
ReStructuredText
.. _core-integration:
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Core Integration
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================
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The main module is named ``ibex_core`` and can be found in ``ibex_core.sv``.
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Below, the instantiation template is given and the parameters and interfaces are described.
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Instantiation Template
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----------------------
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.. code-block:: verilog
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ibex_core #(
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.PMPEnable ( 0 ),
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.PMPGranularity ( 0 ),
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.PMPNumRegions ( 4 ),
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.MHPMCounterNum ( 0 ),
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.MHPMCounterWidth ( 40 ),
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.RV32E ( 0 ),
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.RV32M ( 1 ),
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.RV32B ( 0 ),
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.MultiplierImplementation ( "fast" ),
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.ICache ( 0 ),
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.ICacheECC ( 0 ),
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.SecureIbex ( 0 ),
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.DbgTriggerEn ( 0 ),
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.DmHaltAddr ( 32'h1A110800 ),
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.DmExceptionAddr ( 32'h1A110808 )
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) u_core (
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// Clock and reset
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.clk_i (),
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.rst_ni (),
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.test_en_i (),
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// Configuration
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.hart_id_i (),
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.boot_addr_i (),
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// Instruction memory interface
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.instr_req_o (),
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.instr_gnt_i (),
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.instr_rvalid_i (),
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.instr_addr_o (),
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.instr_rdata_i (),
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.instr_err_i (),
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// Data memory interface
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.data_req_o (),
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.data_gnt_i (),
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.data_rvalid_i (),
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.data_we_o (),
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.data_be_o (),
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.data_addr_o (),
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.data_wdata_o (),
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.data_rdata_i (),
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.data_err_i (),
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// Interrupt inputs
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.irq_software_i (),
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.irq_timer_i (),
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.irq_external_i (),
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.irq_fast_i (),
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.irq_nm_i (),
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// Debug interface
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.debug_req_i (),
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// Special control signals
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.fetch_enable_i (),
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.core_sleep_o ()
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);
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Parameters
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----------
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+------------------------------+-------------+------------+-----------------------------------------------------------------+
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| Name | Type/Range | Default | Description |
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+==============================+=============+============+=================================================================+
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| ``PMPEnable`` | bit | 0 | Enable PMP support |
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+------------------------------+-------------+------------+-----------------------------------------------------------------+
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| ``PMPGranularity`` | int (0..31) | 0 | Minimum granularity of PMP address matching |
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+------------------------------+-------------+------------+-----------------------------------------------------------------+
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| ``PMPNumRegions`` | int (1..16) | 4 | Number implemented PMP regions (ignored if PMPEnable == 0) |
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+------------------------------+-------------+------------+-----------------------------------------------------------------+
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| ``MHPMCounterNum`` | int (0..10) | 0 | Number of performance monitor event counters |
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+------------------------------+-------------+------------+-----------------------------------------------------------------+
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| ``MHPMCounterWidth`` | int (64..1) | 40 | Bit width of performance monitor event counters |
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+------------------------------+-------------+------------+-----------------------------------------------------------------+
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| ``RV32E`` | bit | 0 | RV32E mode enable (16 integer registers only) |
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+------------------------------+-------------+------------+-----------------------------------------------------------------+
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| ``RV32M`` | bit | 1 | M(ultiply) extension enable |
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+------------------------------+-------------+------------+-----------------------------------------------------------------+
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| ``RV32B`` | bit | 0 | *EXPERIMENTAL* - B(itmanipulation) extension enable: |
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| | | | Currently supported Z-extensions: Zbb (base), Zbs (single-bit) |
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| | | | Zbp (bit permutation), Zbe (bit extract/deposit), |
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| | | | Zbf (bit-field place) Zbc (carry-less multiplication) |
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| | | | Zbr (cyclic redundancy check) and Zbt (ternary) |
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+------------------------------+-------------+------------+-----------------------------------------------------------------+
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| ``BranchTargetALU`` | bit | 0 | *EXPERIMENTAL* - Enables branch target ALU removing a stall |
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| | | | cycle from taken branches |
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+------------------------------+-------------+------------+-----------------------------------------------------------------+
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| ``WritebackStage`` | bit | 0 | *EXPERIMENTAL* - Enables third pipeline stage (writeback) |
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| | | | improving performance of loads and stores |
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+------------------------------+-------------+------------+-----------------------------------------------------------------+
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| ``MultiplierImplementation`` | string | "fast" | Multiplicator type: |
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| | | | "slow": multi-cycle slow, |
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| | | | "fast": multi-cycle fast, |
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| | | | "single-cycle": single-cycle |
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+------------------------------+-------------+------------+-----------------------------------------------------------------+
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| ``ICache`` | bit | 0 | *EXPERIMENTAL* Enable instruction cache instead of prefetch |
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| | | | buffer |
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+------------------------------+-------------+------------+-----------------------------------------------------------------+
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| ``ICacheECC`` | bit | 0 | *EXPERIMENTAL* Enable SECDED ECC protection in ICache (if |
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| | | | ICache == 1) |
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+------------------------------+-------------+------------+-----------------------------------------------------------------+
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| ``SecureIbex`` | bit | 0 | *EXPERIMENTAL* Enable various additional features targeting |
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| | | | secure code execution. |
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+------------------------------+-------------+------------+-----------------------------------------------------------------+
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| ``DbgTriggerEn`` | bit | 0 | Enable debug trigger support (one trigger only) |
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+------------------------------+-------------+------------+-----------------------------------------------------------------+
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| ``DmHaltAddr`` | int | 0x1A110800 | Address to jump to when entering Debug Mode |
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+------------------------------+-------------+------------+-----------------------------------------------------------------+
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| ``DmExceptionAddr`` | int | 0x1A110808 | Address to jump to when an exception occurs while in Debug Mode |
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+------------------------------+-------------+------------+-----------------------------------------------------------------+
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Any parameter marked *EXPERIMENTAL* when enabled is not verified to the same standard as the rest of the Ibex core.
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Interfaces
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----------
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+-------------------------+-------------------------+-----+----------------------------------------+
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| Signal(s) | Width | Dir | Description |
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+=========================+=========================+=====+========================================+
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| ``clk_i`` | 1 | in | Clock signal |
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+-------------------------+-------------------------+-----+----------------------------------------+
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| ``rst_ni`` | 1 | in | Active-low asynchronous reset |
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+-------------------------+-------------------------+-----+----------------------------------------+
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| ``test_en_i`` | 1 | in | Test input, enables clock |
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+-------------------------+-------------------------+-----+----------------------------------------+
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| ``hart_id_i`` | 32 | in | Hart ID, usually static, can be read |
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| | | | from :ref:`csr-mhartid` CSR |
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+-------------------------+-------------------------+-----+----------------------------------------+
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| ``boot_addr_i`` | 32 | in | First program counter after reset |
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| | | | = ``boot_addr_i`` + 0x80, |
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| | | | see :ref:`exceptions-interrupts` |
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+-------------------------+-------------------------+-----+----------------------------------------+
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| ``instr_*`` | Instruction fetch interface, see :ref:`instruction-fetch` |
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+-------------------------+------------------------------------------------------------------------+
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| ``data_*`` | Load-store unit interface, see :ref:`load-store-unit` |
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+-------------------------+------------------------------------------------------------------------+
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| ``irq_*`` | Interrupt inputs, see :ref:`exceptions-interrupts` |
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+-------------------------+------------------------------------------------------------------------+
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| ``debug_*`` | Debug interface, see :ref:`debug-support` |
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+-------------------------+-------------------------+-----+----------------------------------------+
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| ``fetch_enable_i`` | 1 | in | When it comes out of reset, the core |
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| | | | will not start fetching and executing |
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| | | | instructions until it sees this pin |
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| | | | set to 1'b1. Once started, it will |
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| | | | continue until the next reset, |
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| | | | regardless of the value of this pin. |
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+-------------------------+-------------------------+-----+----------------------------------------+
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| ``core_sleep_o`` | 1 | out | Core in WFI with no outstanding data |
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| | | | or instruction accesses. Deasserts |
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| | | | if an external event (interrupt or |
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| | | | debug req) wakes the core up |
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+-------------------------+-------------------------+-----+----------------------------------------+
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