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112 lines
5.3 KiB
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112 lines
5.3 KiB
ReStructuredText
Introduction
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============
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.. figure:: images/blockdiagram.svg
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:name: blockdiagram
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Block Diagram
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Ibex is a 2-stage in-order 32b RISC-V processor core.
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Ibex has been designed to be small and efficient.
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Via two parameters, the core is configurable to support four ISA configurations.
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:numref:`blockdiagram` shows a block diagram of the core.
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Standards Compliance
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--------------------
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Ibex is a standards-compliant 32b RISC-V processor.
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It follows these specifications:
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* `RISC-V Instruction Set Manual, Volume I: User-Level ISA, document version 20190608-Base-Ratified (June 8, 2019) <https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMFDQC-and-Priv-v1.11/riscv-spec-20190608.pdf>`_
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* `RISC-V Instruction Set Manual, Volume II: Privileged Architecture, document version 20190608-Base-Ratified (June 8, 2019) <https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMFDQC-and-Priv-v1.11/riscv-privileged-20190608.pdf>`_.
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Ibex implements the Machine ISA version 1.11.
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* `RISC-V External Debug Support, version 0.13.2 <https://content.riscv.org/wp-content/uploads/2019/03/riscv-debug-release.pdf>`_
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Many features in the RISC-V specification are optional, and Ibex can be parametrized to enable or disable some of them.
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Ibex can be parametrized to support either of the following two instruction sets.
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* The RV32I Base Integer Instruction Set, version 2.1
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* The RV32E Base Integer Instruction Set, version 1.9 (draft from June 8, 2019)
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In addition, the following instruction set extensions are available.
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.. list-table:: Ibex Instruction Set Extensions
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:header-rows: 1
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* - Extension
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- Version
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- Configurability
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* - **C**: Standard Extension for Compressed Instructions
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- 2.0
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- always enabled
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* - **M**: Standard Extension for Integer Multiplication and Division
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- 2.0
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- optional
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* - **Zicsr**: Control and Status Register Instructions
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- 2.0
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- always enabled
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* - **Zifencei**: Instruction-Fetch Fence
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- 2.0
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- always enabled
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Most content of the RISC-V privileged specification is optional.
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Ibex currently supports the following features according to the RISC-V Privileged Specification, version 1.11.
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* M-Mode and U-Mode
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* All CSRs listed in :ref:`cs-registers`
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* Performance counters as described in :ref:`performance-counters`
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* Vectorized trap handling as described at :ref:`exceptions-interrupts`
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ASIC Synthesis
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--------------
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ASIC synthesis is supported for Ibex.
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The whole design is completely synchronous and uses positive-edge triggered flip-flops, except for the register file, which can be implemented either with latches or with flip-flops.
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See :ref:`register-file` for more details.
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The core occupies an area of roughly 18.9 kGE when using the latch-based register file and implementing the RV32IMC ISA, or 11.6 kGE when implementing the RV32EC ISA.
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FPGA Synthesis
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--------------
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FPGA synthesis is supported for Ibex when the flip-flop based register file is used.
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Since latches are not well supported on FPGAs, it is crucial to select the flip-flop based register file.
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Contents
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--------
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* :ref:`getting-started` discusses the requirements and initial steps to start using Ibex.
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* :ref:`core-integration` provides the instantiation template and gives descriptions of the design parameters as well as the input and output ports.
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* :ref:`pipeline-details` described the overal pipeline structure.
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* :ref:`instruction-decode-execute` describes how the Instruction Decode and Execute stage works.
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* The instruction and data interfaces of Ibex are explained in :ref:`instruction-fetch` and :ref:`load-store-unit`, respectively.
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* :ref:`icache` describes the optional Instruction Cache.
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* The two register-file flavors are described in :ref:`register-file`.
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* The control and status registers are explained in :ref:`cs-registers`.
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* :ref:`performance-counters` gives an overview of the performance monitors and event counters available in Ibex.
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* :ref:`exceptions-interrupts` deals with the infrastructure for handling exceptions and interrupts,
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* :ref:`pmp` gives a brief overview of PMP support.
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* :ref:`debug-support` gives a brief overview on the debug infrastructure.
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* :ref:`tracer` gives a brief overview of the tracer module.
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* For information regarding formal verification support, check out :ref:`rvfi`.
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* :ref:`examples` gives an overview of how Ibex can be used.
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History
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-------
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Ibex development started in 2015 under the name "Zero-riscy" as part of the `PULP platform <https://pulp-platform.org>`_ for energy-efficient computing.
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Much of the code was developed by simplifying the RV32 CPU core "RI5CY" to demonstrate how small a RISC-V CPU core could actually be `[1] <https://doi.org/10.1109/PATMOS.2017.8106976>`_.
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To make it even smaller, support for the "E" extension was added under the code name "Micro-riscy".
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In the PULP ecosystem, the core is used as the control core for PULP, PULPino and PULPissimo.
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In December 2018 lowRISC took over the development of Zero-riscy and renamed it to Ibex.
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References
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----------
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1. `Schiavone, Pasquale Davide, et al. "Slow and steady wins the race? A comparison of ultra-low-power RISC-V cores for Internet-of-Things applications." 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS 2017) <https://doi.org/10.1109/PATMOS.2017.8106976>`_
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