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9d232d1cde
prim_assert.sv is a file containing assertion macros (defines). Previously, prim_assert.sv was compiled as normal SystemVerilog file. This made the defines available for the whole compilation unit as soon as they were defined. Since all cores using prim_assert depended (in fusesoc) on the lowrisc:prim:assert core, prim_assert was always compiled first, and the defines were visible in subsequent files. All of that is only true if all files end up in one comilation unit. The SV standard states that what makes up a compilation unit is tool-defined, but also states that typically, passing multiple files (or a file list/.f file) to a single tool invocation means that all files end up in one compilation unit; if the tool is called multiple times, then the files end up in separate compilation units. Edalize (the fusesoc backend) doesn't guarantee either behavior, and so it happens that for Vivado, Verilator, Cadence and Synopsys simulators, all files are compiled into a single compilation unit. But for Riviera, each file is a separate compilation unit. To avoid relying on the definition of compilation units, and to do the generally right thing (TM), this commit changes the code to always include the prim_assert.sv file when it is used in a source file. Include guards are introduced in the prim_assert.sv file to avoid defining things twice.
294 lines
9.7 KiB
Systemverilog
294 lines
9.7 KiB
Systemverilog
// Copyright lowRISC contributors.
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// Copyright 2018 ETH Zurich and University of Bologna, see also CREDITS.md.
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// Licensed under the Apache License, Version 2.0, see LICENSE for details.
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// SPDX-License-Identifier: Apache-2.0
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/**
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* Slow Multiplier and Division
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*
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* Baugh-Wooley multiplier and Long Division
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*/
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`include "prim_assert.sv"
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module ibex_multdiv_slow (
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input logic clk_i,
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input logic rst_ni,
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input logic mult_en_i,
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input logic div_en_i,
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input ibex_pkg::md_op_e operator_i,
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input logic [1:0] signed_mode_i,
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input logic [31:0] op_a_i,
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input logic [31:0] op_b_i,
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input logic [33:0] alu_adder_ext_i,
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input logic [31:0] alu_adder_i,
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input logic equal_to_zero,
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output logic [32:0] alu_operand_a_o,
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output logic [32:0] alu_operand_b_o,
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output logic [31:0] multdiv_result_o,
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output logic valid_o
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);
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import ibex_pkg::*;
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logic [ 4:0] multdiv_state_q, multdiv_state_d, multdiv_state_m1;
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typedef enum logic [2:0] {
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MD_IDLE, MD_ABS_A, MD_ABS_B, MD_COMP, MD_LAST, MD_CHANGE_SIGN, MD_FINISH
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} md_fsm_e;
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md_fsm_e md_state_q, md_state_d;
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logic [32:0] accum_window_q, accum_window_d;
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logic [32:0] res_adder_l;
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logic [32:0] res_adder_h;
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logic [32:0] op_b_shift_q, op_b_shift_d;
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logic [32:0] op_a_shift_q, op_a_shift_d;
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logic [32:0] op_a_ext, op_b_ext;
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logic [32:0] one_shift;
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logic [32:0] op_a_bw_pp, op_a_bw_last_pp;
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logic [31:0] b_0;
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logic sign_a, sign_b;
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logic [32:0] next_reminder, next_quotient;
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logic [32:0] op_remainder;
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logic [31:0] op_numerator_q, op_numerator_d;
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logic is_greater_equal;
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logic div_change_sign, rem_change_sign;
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// (accum_window_q + op_a_shift_q)
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assign res_adder_l = alu_adder_ext_i[32:0];
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// (accum_window_q + op_a_shift_q)>>1
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assign res_adder_h = alu_adder_ext_i[33:1];
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always_comb begin
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alu_operand_a_o = accum_window_q;
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multdiv_result_o = div_en_i ? accum_window_q[31:0] : res_adder_l;
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unique case(operator_i)
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MD_OP_MULL: begin
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alu_operand_b_o = op_a_bw_pp;
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end
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MD_OP_MULH: begin
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alu_operand_b_o = (md_state_q == MD_LAST) ? op_a_bw_last_pp : op_a_bw_pp;
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end
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default: begin
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unique case(md_state_q)
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MD_IDLE: begin
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// 0 - B = 0 iff B == 0
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alu_operand_a_o = {32'h0 , 1'b1};
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alu_operand_b_o = {~op_b_i, 1'b1};
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end
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MD_ABS_A: begin
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// ABS(A) = 0 - A
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alu_operand_a_o = {32'h0 , 1'b1};
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alu_operand_b_o = {~op_a_i, 1'b1};
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end
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MD_ABS_B: begin
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// ABS(B) = 0 - B
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alu_operand_a_o = {32'h0 , 1'b1};
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alu_operand_b_o = {~op_b_i, 1'b1};
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end
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MD_CHANGE_SIGN: begin
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// ABS(Quotient) = 0 - Quotient (or Reminder)
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alu_operand_a_o = {32'h0 , 1'b1};
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alu_operand_b_o = {~accum_window_q[31:0], 1'b1};
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end
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default: begin
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// Division
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alu_operand_a_o = {accum_window_q[31:0], 1'b1}; // it contains the reminder
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alu_operand_b_o = {~op_b_shift_q[31:0], 1'b1}; // -denominator two's compliment
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end
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endcase
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end
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endcase
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end
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// The adder in the ALU computes alu_operand_a_o + alu_operand_b_o which means
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// Reminder - Divisor. If Reminder - Divisor >= 0, is_greater_equal is equal to 1,
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// the next Reminder is Reminder - Divisor contained in res_adder_h and the
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// Quotient multdiv_state_q-th bit is set to 1 using the shift register op_b_shift_q.
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assign is_greater_equal = ((accum_window_q[31] ^ op_b_shift_q[31]) == 1'b0) ?
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(res_adder_h[31] == 1'b0) : accum_window_q[31];
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assign one_shift = {32'b0, 1'b1} << multdiv_state_q;
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assign next_reminder = is_greater_equal ? res_adder_h : op_remainder;
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assign next_quotient = is_greater_equal ? op_a_shift_q | one_shift : op_a_shift_q;
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assign b_0 = {32{op_b_shift_q[0]}};
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// build the partial product
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assign op_a_bw_pp = { ~(op_a_shift_q[32] & op_b_shift_q[0]), (op_a_shift_q[31:0] & b_0) };
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assign op_a_bw_last_pp = { (op_a_shift_q[32] & op_b_shift_q[0]), ~(op_a_shift_q[31:0] & b_0) };
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assign sign_a = op_a_i[31] & signed_mode_i[0];
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assign sign_b = op_b_i[31] & signed_mode_i[1];
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assign op_a_ext = {sign_a, op_a_i};
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assign op_b_ext = {sign_b, op_b_i};
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// division
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assign op_remainder = accum_window_q[32:0];
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assign multdiv_state_m1 = multdiv_state_q - 5'h1;
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assign div_change_sign = sign_a ^ sign_b;
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assign rem_change_sign = sign_a;
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always_ff @(posedge clk_i or negedge rst_ni) begin : proc_multdiv_state_q
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if (!rst_ni) begin
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multdiv_state_q <= 5'h0;
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accum_window_q <= 33'h0;
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op_b_shift_q <= 33'h0;
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op_a_shift_q <= 33'h0;
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op_numerator_q <= 32'h0;
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md_state_q <= MD_IDLE;
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end else begin
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multdiv_state_q <= multdiv_state_d;
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accum_window_q <= accum_window_d;
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op_b_shift_q <= op_b_shift_d;
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op_a_shift_q <= op_a_shift_d;
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op_numerator_q <= op_numerator_d;
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md_state_q <= md_state_d;
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end
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end
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always_comb begin
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multdiv_state_d = multdiv_state_q;
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accum_window_d = accum_window_q;
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op_b_shift_d = op_b_shift_q;
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op_a_shift_d = op_a_shift_q;
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op_numerator_d = op_numerator_q;
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md_state_d = md_state_q;
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if (mult_en_i || div_en_i) begin
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unique case(md_state_q)
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MD_IDLE: begin
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unique case(operator_i)
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MD_OP_MULL: begin
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op_a_shift_d = op_a_ext << 1;
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accum_window_d = { ~(op_a_ext[32] & op_b_i[0]),
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op_a_ext[31:0] & {32{op_b_i[0]}} };
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op_b_shift_d = op_b_ext >> 1;
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md_state_d = MD_COMP;
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end
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MD_OP_MULH: begin
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op_a_shift_d = op_a_ext;
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accum_window_d = { 1'b1, ~(op_a_ext[32] & op_b_i[0]),
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op_a_ext[31:1] & {31{op_b_i[0]}} };
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op_b_shift_d = op_b_ext >> 1;
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md_state_d = MD_COMP;
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end
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MD_OP_DIV: begin
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// Check if the Denominator is 0
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// quotient for division by 0
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accum_window_d = {33{1'b1}};
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md_state_d = equal_to_zero ? MD_FINISH : MD_ABS_A;
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end
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default: begin
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// Check if the Denominator is 0
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// reminder for division by 0
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accum_window_d = op_a_ext;
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md_state_d = equal_to_zero ? MD_FINISH : MD_ABS_A;
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end
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endcase
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multdiv_state_d = 5'd31;
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end
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MD_ABS_A: begin
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// quotient
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op_a_shift_d = '0;
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// A abs value
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op_numerator_d = sign_a ? alu_adder_i : op_a_i;
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md_state_d = MD_ABS_B;
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end
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MD_ABS_B: begin
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// reminder
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accum_window_d = { 32'h0, op_numerator_q[31]};
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// B abs value
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op_b_shift_d = sign_b ? alu_adder_i : op_b_i;
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md_state_d = MD_COMP;
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end
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MD_COMP: begin
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multdiv_state_d = multdiv_state_m1;
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unique case(operator_i)
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MD_OP_MULL: begin
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accum_window_d = res_adder_l;
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op_a_shift_d = op_a_shift_q << 1;
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op_b_shift_d = op_b_shift_q >> 1;
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end
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MD_OP_MULH: begin
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accum_window_d = res_adder_h;
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op_a_shift_d = op_a_shift_q;
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op_b_shift_d = op_b_shift_q >> 1;
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end
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default: begin
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accum_window_d = {next_reminder[31:0], op_numerator_q[multdiv_state_m1]};
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op_a_shift_d = next_quotient;
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end
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endcase
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md_state_d = (multdiv_state_q == 5'd1) ? MD_LAST : MD_COMP;
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end
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MD_LAST: begin
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unique case(operator_i)
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MD_OP_MULL: begin
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accum_window_d = res_adder_l;
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md_state_d = MD_IDLE;
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end
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MD_OP_MULH: begin
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accum_window_d = res_adder_l;
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md_state_d = MD_IDLE;
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end
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MD_OP_DIV: begin
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// this time we save the quotient in accum_window_q since we do not need anymore the
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// reminder
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accum_window_d = next_quotient;
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md_state_d = MD_CHANGE_SIGN;
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end
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default: begin
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// this time we do not save the quotient anymore since we need only the reminder
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accum_window_d = {1'b0, next_reminder[31:0]};
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md_state_d = MD_CHANGE_SIGN;
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end
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endcase
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end
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MD_CHANGE_SIGN: begin
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md_state_d = MD_FINISH;
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unique case(operator_i)
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MD_OP_DIV:
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accum_window_d = (div_change_sign) ? alu_adder_i : accum_window_q;
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default:
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accum_window_d = (rem_change_sign) ? alu_adder_i : accum_window_q;
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endcase
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end
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MD_FINISH: begin
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md_state_d = MD_IDLE;
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end
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default: begin
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md_state_d = MD_IDLE;
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end
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endcase // md_state_q
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end
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end
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assign valid_o = (md_state_q == MD_FINISH) |
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(md_state_q == MD_LAST &
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(operator_i == MD_OP_MULL |
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operator_i == MD_OP_MULH));
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// State must be valid.
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`ASSERT(IbexMultDivStateValid, md_state_q inside {
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MD_IDLE, MD_ABS_A, MD_ABS_B, MD_COMP, MD_LAST, MD_CHANGE_SIGN, MD_FINISH
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}, clk_i, !rst_ni)
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endmodule // ibex_mult
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