Tom Roberts 48f11c6733 [rtl] Add bus integrity checking ... Extra bits are added alongside read/write data for the instruction and data buses to facilitate data integrity checking. Ibex testbench extended to generate the expected bits. All other top-levels modified to add the new signals (which are mostly ignored). Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>		2021-08-26 16:55:26 +01:00
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fpga/artya7	[rtl] Add bus integrity checking	2021-08-26 16:55:26 +01:00
simple_system	[rtl] Add bus integrity checking	2021-08-26 16:55:26 +01:00
sw	[sw/fpga] coremark/link.ld update for FPGA sim	2021-08-03 16:51:16 +01:00