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77 lines
3.2 KiB
Systemverilog
77 lines
3.2 KiB
Systemverilog
////////////////////////////////////////////////////////////////////////////////
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// Company: IIS @ ETHZ - Federal Institute of Technology //
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// //
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// Engineer: Matthias Baer - baermatt@student.ethz.ch //
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// //
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// Additional contributions by: //
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// Andreas Traber - atraber@student.ethz.ch //
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// //
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// //
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// Create Date: 19/09/2013 //
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// Design Name: Vectorial Multiplier and MAC //
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// Module Name: mult.sv //
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// Project Name: RI5CY //
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// Language: SystemVerilog //
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// //
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// Description: Advanced MAC unit for PULP. //
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// //
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// //
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// Revision: //
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// Revision v0.1 - File Created //
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// Revision v0.2 - (Oct 30th 2014) Added MAC to the multiplier //
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// Revision v0.3 - (Jan 21th 2015) Changed to a 32 bit result for //
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// multiplications, added vectorial support and subword //
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// selection. There are no flags for multiplications anymore! //
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// //
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// //
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////////////////////////////////////////////////////////////////////////////////
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`include "defines.sv"
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module riscv_mult
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(
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input logic mac_en_i,
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input logic vector_mode_i,
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input logic [1:0] sel_subword_i,
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input logic [1:0] signed_mode_i,
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input logic [31:0] op_a_i,
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input logic [31:0] op_b_i,
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input logic [31:0] mac_i,
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output logic [31:0] result_o
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);
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logic [31:0] op_a_sel;
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logic [31:0] op_b_sel;
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logic [31:0] mac_int;
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// perform subword selection and sign extensions
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always_comb
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begin
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op_a_sel = op_a_i;
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op_b_sel = op_b_i;
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if(vector_mode_i)
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begin
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if(sel_subword_i[1] == 1'b1)
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op_a_sel[15:0] = op_a_i[31:16];
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else
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op_a_sel[15:0] = op_a_i[15:0];
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if(sel_subword_i[0] == 1'b1)
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op_b_sel[15:0] = op_b_i[31:16];
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else
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op_b_sel[15:0] = op_b_i[15:0];
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op_a_sel[31:16] = {16{signed_mode_i[1] & op_a_sel[15]}};
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op_b_sel[31:16] = {16{signed_mode_i[0] & op_b_sel[15]}};
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end
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end
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assign mac_int = (mac_en_i == 1'b1) ? mac_i : 32'b0;
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assign result_o = mac_int + op_a_sel * op_b_sel;
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endmodule
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