Tom Roberts a88f5eb912 [rtl] Add dual core lockstep option ... Note that the alert output is tied off for now until an option is added to reset all registers (otherwise there will be X propagation). Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>		2021-04-07 12:07:38 +01:00
..
images	Restructure documentation	2020-09-28 22:30:00 +01:00
pdfs	[doc] Add ePMP information	2021-02-01 12:22:49 +00:00
cs_registers.rst	[doc] Fix table rendering for mseccfg	2021-03-19 10:51:49 +00:00
debug.rst	Add support for additional HW breakpoints	2020-10-19 13:20:08 +02:00
exception_interrupts.rst	Restructure documentation	2020-09-28 22:30:00 +01:00
history.rst	Restructure documentation	2020-09-28 22:30:00 +01:00
icache.rst	[rtl] Add a new top level plus wiring	2021-04-07 12:07:38 +01:00
index.rst	Restructure documentation	2020-09-28 22:30:00 +01:00
instruction_decode_execute.rst	Restructure documentation	2020-09-28 22:30:00 +01:00
instruction_fetch.rst	Restructure documentation	2020-09-28 22:30:00 +01:00
load_store_unit.rst	Restructure documentation	2020-09-28 22:30:00 +01:00
performance_counters.rst	Restructure documentation	2020-09-28 22:30:00 +01:00
pipeline_details.rst	Restructure documentation	2020-09-28 22:30:00 +01:00
pmp.rst	[doc] Add ePMP information	2021-02-01 12:22:49 +00:00
register_file.rst	Restructure documentation	2020-09-28 22:30:00 +01:00
rvfi.rst	Restructure documentation	2020-09-28 22:30:00 +01:00
security.rst	[rtl] Add dual core lockstep option	2021-04-07 12:07:38 +01:00
tracer.rst	[rtl] Add a new top level plus wiring	2021-04-07 12:07:38 +01:00
verification.rst	[doc] Update dependency descriptions for Spike/OVPsim	2021-01-25 17:41:40 +00:00