Tobias Wölfel 7032df0d8b [formal] Read Verilog files in Yosys ... All files read at this point should be Verilog and not SystemVerilog. Do not use the SystemVerilog specifier for reading files.		2021-07-14 11:02:46 +01:00
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data_ind_timing	[formal] Add check for multdiv cycle consumption	2020-09-16 16:30:20 +01:00
icache	[dv] Fix icache formal tb after recent parameter changes	2021-06-15 15:03:08 +01:00
riscv-formal	[formal] Read Verilog files in Yosys	2021-07-14 11:02:46 +01:00
.gitignore	[formal] Create Ibex Verilog source	2020-05-25 16:47:25 +01:00