ganoam 1aa4d5a32b [bitmanip] Optimizations and Parametrization ... This commit contains some final optimizations regarding the bit manipulation extension as well as the parametrization into a balanced version and a full performance version. Balanced Version: * Supports ZBB, ZBS, ZBF and ZBT extensions * Dual cycle instructions: ror[i], rol, cmov, cmix fsl, fsr[i] * Everything else completes in a single cycle. Full Version: * Supports all 32b sub extensions. * Dual cycle instructions: ror[i], rol, cmov, cmix fsl, fsr[i], crc32[c], bext, bdep * Everything else completes in a single cycle. Notable Changes: * bext/bdep are now multi-cycle: Sharing additional register with multiplier module * grev/gorc instructions are implemented in separate structures rather than sharing the shifter or butterfly network. * Speed up decision on using rs1 or rs3 for alu_operand_a by introducing single-bit register, to identify ternary instructions in their first cycle. * Introduce enumerated parameter to chose bit manipulation implementation Signed-off-by: ganoam <gnoam@live.com>		2020-06-26 14:43:24 +02:00
..
fpga/artya7	Merge pull request #624 from ganoam/fpga-opt-perf-mon-pr	2020-03-06 12:49:51 +01:00
simple_system	[bitmanip] Optimizations and Parametrization	2020-06-26 14:43:24 +02:00
sw	[sw] Fix typo in simple system exception handler	2020-06-02 13:45:46 +01:00