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c0636dcbde
Here's a high-level overview of what this commit does: - Compiles Sail into SystemVerilog including patchin compiler bugs - Create a TCL file that tells JasperGold what to prove and assume - Check memory operations modelling the LSU Most of these properties now prove without time-bound on the response from memory due to alternative LSUs - Check memory even with Smepmp errors: Continues on top of https://github.com/riscv/sail-riscv/pull/196 - CSR verification - Checks for instruction types such as B-Type, I-Type, R-Type - Check illegal instructions and WFI instructions - Using psgen language for proof generation - Documentation on how to use the setup - Wrap around proof that proves instructions executed in a row still match the specification. - Liveness proof to guarantee instructions will retire within a upper bound of cycles. All of these proofs make heavy use of the concept of k-induction. All the different properties and steps are necessary to help the tool get the useful properties it needs to prove the next step. The instruction correctness, wrap-around and liveness all give us increased confidence that Ibex is trace-equivalent to Sail. Throughout this process an issue was found in Ibex where the pipeline was not flushing properly on changing PMP registers using clear: #2193 Alternative LSUs: This makes all top level memory properties prove quickly and at a low proof effort (1 or 2-induction). Three 'alternative LSUs' representing three stages of memory instructions: 1. Before the first response is received, in the EX stage 2. After the first response is received, but not the second grant, also in the EX stage 3. Before the last response is received in the WB stage. In each case we ask 'if the response came now, would the result be correct?'. Similar is applied for CSRs/PC though less directly. This is particularly interesting (read: ugly) in the case of a PMP error wbexc_exists makes Wrap properties fast to prove. The bottleneck becomes SpecPastNoWbexcPC, which fails only due to a bug. See the comment in riscv.proof. Co-authored-by: Marno van der Maas <mvdmaas+git@lowrisc.org> Signed-off-by: Louis-Emile Ploix <louis-emile.ploix@lowrisc.org>
113 lines
3.1 KiB
Python
113 lines
3.1 KiB
Python
# Copyright lowRISC contributors.
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# Copyright 2024 University of Oxford, see also CREDITS.md.
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# Licensed under the Apache License, Version 2.0, see LICENSE for details.
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# Original author: Louis-Emile Ploix
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# SPDX-License-Identifier: Apache-2.0
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# This script is called from the Makefile.
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# Essentially it is a way to enable and disable instructions from the Sail specification to make proofs easier.
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import json
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import re
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import sys
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with open("instrs.json", "r") as f:
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INSTRS = set(json.load(f))
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class SpecConfig:
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def __init__(self):
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self.instrs = set()
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def add(self, *instrs):
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for instr in instrs:
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assert instr in INSTRS
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self.instrs.add(instr)
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def add_all(self):
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self.instrs = INSTRS
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def add_noncompressed(self):
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self.instrs = {x for x in INSTRS if not x.startswith("C_")}
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def remove(self, instr):
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assert instr in INSTRS
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self.instrs.discard(instr)
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def make_sail_unreachables(self):
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return " ".join(f"-sv_unreachable execute_{instr}" for instr in INSTRS.difference(self.instrs))
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def make_sv_header(self):
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return "\n".join([
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"`ifndef SPEC_INSTRS",
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"`define SPEC_INSTRS",
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"",
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*[f"`define SPEC_{instr.upper()} {int(instr in self.instrs)}" for instr in INSTRS],
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"",
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"`endif"
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])
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def add_jmps(self):
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self.add("RISCV_JAL", "RISCV_JALR")
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def add_itype(self):
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self.add("ITYPE")
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self.add("SHIFTIOP")
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def add_rtype(self):
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self.add("RTYPE")
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def add_fences(self):
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self.add("FENCE", "FENCEI")
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def add_loads(self):
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self.add("LOAD")
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def add_stores(self):
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self.add("STORE")
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def add_mtypes(self):
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self.add("MUL", "DIV", "REM")
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def add_illegal(self, extra=True):
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self.add("ILLEGAL", "C_ILLEGAL")
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if extra:
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self.add("CSR")
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self.add("MRET", "WFI")
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def add_system(self):
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self.add("ECALL", "EBREAK", "MRET", "WFI")
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def add_csr(self):
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self.add("CSR")
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def add_utypes(self):
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self.add("UTYPE")
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def add_btypes(self):
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self.add("BTYPE")
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conf = SpecConfig()
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conf.add_noncompressed()
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if len(sys.argv) > 1:
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if sys.argv[1] == "unreachables":
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print(conf.make_sail_unreachables())
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elif sys.argv[1] == "header":
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print(conf.make_sv_header())
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elif sys.argv[1] == "unreachable_loc_hack":
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with open("build/ibexspec.sv", "r") as f:
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c = f.read()
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c = c.replace(
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"sail_reached_unreachable = 1;",
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"begin sail_reached_unreachable = 1; sail_reached_unreachable_loc = `__LINE__; end"
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).replace(
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"sail_reached_unreachable = 0;",
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"begin sail_reached_unreachable = 0; sail_reached_unreachable_loc = -1; end"
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).replace(
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"bit sail_reached_unreachable;",
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"bit sail_reached_unreachable;\n\tlogic [31:0] sail_reached_unreachable_loc;"
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)
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with open("build/ibexspec.sv", "w") as f:
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f.write(c)
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else:
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print("Intended usage is to run make sv")
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