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c0636dcbde
Here's a high-level overview of what this commit does: - Compiles Sail into SystemVerilog including patchin compiler bugs - Create a TCL file that tells JasperGold what to prove and assume - Check memory operations modelling the LSU Most of these properties now prove without time-bound on the response from memory due to alternative LSUs - Check memory even with Smepmp errors: Continues on top of https://github.com/riscv/sail-riscv/pull/196 - CSR verification - Checks for instruction types such as B-Type, I-Type, R-Type - Check illegal instructions and WFI instructions - Using psgen language for proof generation - Documentation on how to use the setup - Wrap around proof that proves instructions executed in a row still match the specification. - Liveness proof to guarantee instructions will retire within a upper bound of cycles. All of these proofs make heavy use of the concept of k-induction. All the different properties and steps are necessary to help the tool get the useful properties it needs to prove the next step. The instruction correctness, wrap-around and liveness all give us increased confidence that Ibex is trace-equivalent to Sail. Throughout this process an issue was found in Ibex where the pipeline was not flushing properly on changing PMP registers using clear: #2193 Alternative LSUs: This makes all top level memory properties prove quickly and at a low proof effort (1 or 2-induction). Three 'alternative LSUs' representing three stages of memory instructions: 1. Before the first response is received, in the EX stage 2. After the first response is received, but not the second grant, also in the EX stage 3. Before the last response is received in the WB stage. In each case we ask 'if the response came now, would the result be correct?'. Similar is applied for CSRs/PC though less directly. This is particularly interesting (read: ugly) in the case of a PMP error wbexc_exists makes Wrap properties fast to prove. The bottleneck becomes SpecPastNoWbexcPC, which fails only due to a bug. See the comment in riscv.proof. Co-authored-by: Marno van der Maas <mvdmaas+git@lowrisc.org> Signed-off-by: Louis-Emile Ploix <louis-emile.ploix@lowrisc.org>
80 lines
4.7 KiB
Systemverilog
80 lines
4.7 KiB
Systemverilog
// Copyright lowRISC contributors.
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// Copyright 2024 University of Oxford, see also CREDITS.md.
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// Licensed under the Apache License, Version 2.0, see LICENSE for details.
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// Original author: Louis-Emile Ploix
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// SPDX-License-Identifier: Apache-2.0
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/*
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Provides stubs (mostly) for the native functions the Sail expects to see, mostly
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handling config stuff.
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*/
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function automatic logic[127:0] sail_emod_int(logic[127:0] x, logic[127:0] y);
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// This one is unsigned, but the rest should be signed
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return x % y;
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endfunction
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function automatic logic[127:0] sail_pow_int(logic[127:0] x, logic[127:0] y);
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// These are Sail integers, so operations on them should be signed
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return signed'(x) ** signed'(y);
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endfunction
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function automatic logic[127:0] sail_tmod_int(logic[127:0] x, logic[127:0] y);
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return signed'(x) % signed'(y);
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endfunction
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function automatic logic[127:0] sail_tdiv_int(logic[127:0] x, logic[127:0] y);
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return signed'(x) / signed'(y);
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endfunction
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function automatic sail_bits sail_shift_bits_left(sail_bits x, sail_bits y);
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return {x.size, x.bits << y.bits};
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endfunction
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function automatic sail_bits sail_shift_bits_right(sail_bits x, sail_bits y);
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return {x.size, x.bits >> y.bits};
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endfunction
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function automatic sail_unit sail_decimal_string_of_bits(logic [11:0] x);
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return SAIL_UNIT;
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endfunction
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function automatic logic sail_elf_tohost(sail_unit u); return 0; endfunction
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function automatic logic sail_get_config_print_mem(sail_unit u); return 0; endfunction
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function automatic logic sail_get_config_print_platform(sail_unit u); return 0; endfunction
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function automatic logic sail_get_config_print_reg(sail_unit u); return 0; endfunction
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function automatic logic sail_get_config_print_instr(sail_unit u); return 0; endfunction
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function automatic logic sail_get_config_print_exception(sail_unit u); return 0; endfunction
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function automatic logic[31:0] sail_plat_clint_base(sail_unit u); return 0; endfunction
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function automatic logic[31:0] sail_plat_clint_size(sail_unit u); return 0; endfunction
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function automatic logic sail_plat_enable_dirty_update(sail_unit u); return 0; endfunction
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function automatic logic sail_plat_enable_misaligned_access(sail_unit u); return 1; endfunction
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function automatic logic sail_plat_enable_pmp(sail_unit u); return 0; endfunction
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function automatic sail_unit sail_platform_barrier(t_barrier_kind k); return SAIL_UNIT; endfunction
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function automatic sail_unit sail_platform_write_mem_ea(
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t_write_kind a, logic [63:0] b, sail_bits c, logic [127:0] d
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); return SAIL_UNIT; endfunction
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function automatic logic[15:0] sail_plat_get_16_random_bits(sail_unit u); return 0; endfunction
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function automatic logic sail_plat_htif_tohost(sail_unit u); return 0; endfunction
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function automatic logic sail_plat_mtval_has_illegal_inst_bits(sail_unit u); return 1; endfunction
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function automatic logic[31:0] sail_plat_ram_base(sail_unit u); return 0; endfunction
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function automatic logic[31:0] sail_plat_ram_size(sail_unit u); return 0; endfunction
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function automatic logic[31:0] sail_plat_rom_base(sail_unit u); return 0; endfunction
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function automatic logic[31:0] sail_plat_rom_size(sail_unit u); return 0; endfunction
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function automatic sail_unit sail_plat_term_write(logic[7:0] u); return SAIL_UNIT; endfunction
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function automatic sail_unit sail_print_mem_access(sail_unit u); return SAIL_UNIT; endfunction
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function automatic sail_unit sail_print_platform(sail_unit u); return SAIL_UNIT; endfunction
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function automatic sail_unit sail_print_reg(sail_unit u); return SAIL_UNIT; endfunction
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function automatic sail_unit sail_string_of_int(logic[127:0] u); return SAIL_UNIT; endfunction
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function automatic logic sail_sys_enable_fdext(sail_unit u); return 0; endfunction
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function automatic logic sail_sys_enable_rvc(sail_unit u); return 1; endfunction
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function automatic logic sail_sys_enable_writable_misa(sail_unit u); return 0; endfunction
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function automatic logic sail_sys_enable_zfinx(sail_unit u); return 0; endfunction
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function automatic sail_unit sail_cancel_reservation(sail_unit u); return SAIL_UNIT; endfunction
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function automatic logic[31:0] sail_plat_uart_base(sail_unit u); return 0; endfunction
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function automatic logic[31:0] sail_plat_uart_size(sail_unit u); return 0; endfunction
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function automatic logic[6:0] sail_sys_pmp_count(sail_unit u); return 7'd4; endfunction
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function automatic logic[6:0] sail_sys_pmp_max_count(sail_unit u); return 7'd16; endfunction
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function automatic sail_unit sail_load_reservation(logic[31:0] u); return SAIL_UNIT; endfunction
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function automatic logic sail_speculate_conditional(sail_unit u); return 0; endfunction
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function automatic logic[63:0] sail_sys_pmp_grain(sail_unit u); return 0; endfunction
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function automatic logic sail_sys_enable_writable_fiom(sail_unit u); return 0; endfunction
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