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231 lines
9.6 KiB
Systemverilog
231 lines
9.6 KiB
Systemverilog
////////////////////////////////////////////////////////////////////////////////
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// Company: IIS @ ETHZ - Federal Institute of Technology //
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// //
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// Engineer: Sven Stucki - svstucki@student.ethz.ch //
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// //
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// Additional contributions by: //
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// //
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// //
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// Create Date: 10/06/2015 //
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// Design Name: Compressed instruction decoder //
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// Module Name: compressed_decoder.sv //
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// Project Name: RI5CY //
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// Language: SystemVerilog //
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// //
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// Description: Decodes RISC-V compressed instructions into their RV32 //
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// equivalent. This module is fully combinatorial. //
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// //
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// Revision: //
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// Revision v0.1 - File Created //
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// //
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// //
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////////////////////////////////////////////////////////////////////////////////
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`include "defines.sv"
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module riscv_compressed_decoder
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(
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input logic [31:0] instr_i,
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output logic [31:0] instr_o,
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output logic is_compressed_o,
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output logic illegal_instr_o
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);
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//////////////////////////////////////////////////////////////////////////////////////////////////////
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// ____ _ ____ _ //
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// / ___|___ _ __ ___ _ __ _ __ ___ ___ ___ ___ __| | | _ \ ___ ___ ___ __| | ___ _ __ //
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// | | / _ \| '_ ` _ \| '_ \| '__/ _ \/ __/ __|/ _ \/ _` | | | | |/ _ \/ __/ _ \ / _` |/ _ \ '__| //
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// | |__| (_) | | | | | | |_) | | | __/\__ \__ \ __/ (_| | | |_| | __/ (_| (_) | (_| | __/ | //
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// \____\___/|_| |_| |_| .__/|_| \___||___/___/\___|\__,_| |____/ \___|\___\___/ \__,_|\___|_| //
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// |_| //
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//////////////////////////////////////////////////////////////////////////////////////////////////////
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always_comb
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begin
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illegal_instr_o = 1'b0;
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instr_o = 'X;
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unique case (instr_i[1:0])
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// C0
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2'b00: begin
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unique case (instr_i[15:13])
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3'b000: begin
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// c.addi4spn -> addi rd', x2, imm
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instr_o = {2'b0, instr_i[10:7], instr_i[12:11], instr_i[5], instr_i[6], 2'b00, 5'h02, 3'b000, 2'b01, instr_i[4:2], `OPCODE_OPIMM};
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if (instr_i[12:5] == 8'b0) illegal_instr_o = 1'b1;
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end
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3'b010: begin
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// c.lw -> lw rd', imm(rs1')
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instr_o = {5'b0, instr_i[5], instr_i[12:10], instr_i[6], 2'b00, 2'b01, instr_i[9:7], 3'b010, 2'b01, instr_i[4:2], `OPCODE_LOAD};
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end
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3'b110: begin
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// c.sw -> sw rs2', imm(rs1')
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instr_o = {5'b0, instr_i[5], instr_i[12], 2'b01, instr_i[4:2], 2'b01, instr_i[9:7], 3'b010, instr_i[11:10], instr_i[6], 2'b00, `OPCODE_STORE};
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end
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default: begin
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illegal_instr_o = 1'b1;
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end
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endcase
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end
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// C1
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2'b01: begin
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unique case (instr_i[15:13])
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3'b000: begin
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// c.addi -> addi rd, rd, nzimm
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// c.nop
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instr_o = {{6 {instr_i[12]}}, instr_i[12], instr_i[6:2], instr_i[11:7], 3'b0, instr_i[11:7], `OPCODE_OPIMM};
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end
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3'b001, 3'b101: begin
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// 001: c.jal -> jal x1, imm
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// 101: c.j -> jal x0, imm
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instr_o = {instr_i[12], instr_i[8], instr_i[10:9], instr_i[6], instr_i[7], instr_i[2], instr_i[11], instr_i[5:3], {9 {instr_i[12]}}, 4'b0, ~instr_i[15], `OPCODE_JAL};
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end
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3'b010: begin
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// c.li -> addi rd, x0, nzimm
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instr_o = {{6 {instr_i[12]}}, instr_i[12], instr_i[6:2], 5'b0, 3'b0, instr_i[11:7], `OPCODE_OPIMM};
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if (instr_i[11:7] == 5'b0) illegal_instr_o = 1'b1;
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end
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3'b011: begin
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// c.lui -> lui rd, imm
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instr_o = {{15 {instr_i[12]}}, instr_i[6:2], instr_i[11:7], `OPCODE_LUI};
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if (instr_i[11:7] == 5'h02) begin
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// c.addi16sp -> addi x2, x2, nzimm
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instr_o = {{3 {instr_i[12]}}, instr_i[4:3], instr_i[5], instr_i[2], instr_i[6], 4'b0, 5'h02, 3'b000, 5'h02, `OPCODE_OPIMM};
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end else if (instr_i[11:7] == 5'b0) begin
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illegal_instr_o = 1'b1;
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end
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if ({instr_i[12], instr_i[6:2]} == 6'b0) illegal_instr_o = 1'b1;
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end
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3'b100: begin
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unique case (instr_i[11:10])
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2'b00,
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2'b01: begin
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// 00: c.srli -> srli rd, rd, shamt
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// 01: c.srai -> srai rd, rd, shamt
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instr_o = {1'b0, instr_i[10], 5'b0, instr_i[6:2], 2'b01, instr_i[9:7], 3'b101, 2'b01, instr_i[9:7], `OPCODE_OPIMM};
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if (instr_i[12] == 1'b1) illegal_instr_o = 1'b1;
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if (instr_i[6:2] == 5'b0) illegal_instr_o = 1'b1;
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if (instr_i[9:7] == 5'b0) illegal_instr_o = 1'b1;
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end
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2'b10: begin
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// c.andi -> andi rd, rd, imm
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instr_o = {{6 {instr_i[12]}}, instr_i[12], instr_i[6:2], 2'b01, instr_i[9:7], 3'b111, 2'b01, instr_i[9:7], `OPCODE_OPIMM};
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end
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2'b11: begin
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unique case ({instr_i[12], instr_i[6:5]})
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3'b001,
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3'b100,
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3'b101,
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3'b110,
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3'b111: begin
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// 001: c.sll -> sll rd', rd', rs2'
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// 100: c.xor -> xor rd', rd', rs2'
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// 101: c.srl -> srl rd', rd', rs2'
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// 110: c.or -> or rd', rd', rs2'
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// 111: c.and -> and rd', rd', rs2'
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instr_o = {7'b0, 2'b01, instr_i[4:2], 2'b01, instr_i[9:7], instr_i[12], instr_i[6:5], 2'b01, instr_i[9:7], `OPCODE_OP};
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end
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3'b000,
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3'b010: begin
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// 000: c.addw
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// 010: c.subw
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illegal_instr_o = 1'b1;
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end
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3'b011: begin
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// c.sub -> sub rd', rd', rs2'
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instr_o = {2'b01, 5'b0, 2'b01, instr_i[4:2], 2'b01, instr_i[9:7], 3'b000, 2'b01, instr_i[9:7], `OPCODE_OP};
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end
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endcase
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end
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endcase
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end
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3'b110, 3'b111: begin
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// 0: c.beqz -> beq rs1', x0, imm
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// 1: c.bnez -> bne rs1', x0, imm
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instr_o = {{4 {instr_i[12]}}, instr_i[6:5], instr_i[2], 5'b0, 2'b01, instr_i[9:7], 2'b00, instr_i[13], instr_i[11:10], instr_i[4:3], instr_i[12], `OPCODE_BRANCH};
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end
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default: begin
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illegal_instr_o = 1'b1;
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end
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endcase
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end
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// C2
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2'b10: begin
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unique case (instr_i[15:13])
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3'b000: begin
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// c.slli -> slli rd, rd, shamt
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instr_o = {7'b0, instr_i[6:2], instr_i[11:7], 3'b001, instr_i[11:7], `OPCODE_OPIMM};
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if (instr_i[11:7] == 5'b0) illegal_instr_o = 1'b1;
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if (instr_i[12] == 1'b1 || instr_i[6:2] == 5'b0) illegal_instr_o = 1'b1;
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end
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3'b010: begin
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// c.lwsp -> lw rd, imm(x2)
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instr_o = {4'b0, instr_i[3:2], instr_i[12], instr_i[6:4], 2'b00, 5'h02, 3'b010, instr_i[11:7], `OPCODE_LOAD};
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if (instr_i[11:7] == 5'b0) illegal_instr_o = 1'b1;
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end
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3'b100: begin
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if (instr_i[12] == 1'b0) begin
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// c.mv -> add rd/rs1, x0, rs2
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instr_o = {7'b0, instr_i[6:2], 5'b0, 3'b0, instr_i[11:7], `OPCODE_OP};
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if (instr_i[6:2] == 5'b0) begin
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// c.jr -> jalr x0, rd/rs1, 0
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instr_o = {12'b0, instr_i[11:7], 3'b0, 5'b0, `OPCODE_JALR};
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end
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end else begin
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// c.add -> add rd, rd, rs2
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instr_o = {7'b0, instr_i[6:2], instr_i[11:7], 3'b0, instr_i[11:7], `OPCODE_OP};
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if (instr_i[11:7] == 5'b0) begin
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// c.ebreak -> ebreak
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instr_o = {32'h00_10_00_73};
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if (instr_i[6:2] != 5'b0)
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illegal_instr_o = 1'b1;
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end else if (instr_i[6:2] == 5'b0) begin
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// c.jalr -> jalr x1, rs1, 0
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instr_o = {12'b0, instr_i[11:7], 3'b000, 5'b00001, `OPCODE_JALR};
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end
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end
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end
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3'b110: begin
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// c.swsp -> sw rs2, imm(x2)
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instr_o = {4'b0, instr_i[8:7], instr_i[12], instr_i[6:2], 5'h02, 3'b010, instr_i[11:9], 2'b00, `OPCODE_STORE};
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end
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default: begin
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illegal_instr_o = 1'b1;
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end
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endcase
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end
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default: begin
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// 32 bit (or more) instruction
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instr_o = instr_i;
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end
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endcase
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end
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assign is_compressed_o = (instr_i[1:0] != 2'b11);
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endmodule
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