Pirmin Vogel 9738b6c703 [rtl] Rework core_busy signals, remove feedback to clk ... This commit reworks the generation of the `core_busy` signal used to control the main clock gate of the core. Without this commit, the controller generates a separate `first_fetch` signal only asserted in the FIRST_FETCH state that directly controls `core_busy` and thus the main clock gate. This is problematic as it introduces a feedback to from the controller state into the clock. This commit removes the problematic signal and changes the generation of `ctrl_busy` in the FIRST_FETCH state of the controller. This signal is now used to control the main clock gate in all states (previously all except FIRST_FETCH) but it gets registered, thus it does not introduce the feedback into the clock. This resolves lowRISC/ibex#211. Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>		2019-11-14 12:55:16 +01:00
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verilator_waiver.vlt	[rtl] Rework core_busy signals, remove feedback to clk	2019-11-14 12:55:16 +01:00