Rupert Swarbrick e9872889bf Split have_instr definition out of always block in if_stage ... This should cause no functional change, but avoids a seeming combinatorial loop reported by Verilator. The seeming loop is because the always_comb process that contained have_instr is sensitive to if_id_pipe_reg_we but that process wrote the have_instr signal, which is used in the continuous assignment to if_id_pipe_reg_we later on.		2020-03-02 12:42:17 +00:00
..
ibex_alu.sv	[rtl] Add multdiv_sel signal to decode	2020-01-31 09:32:20 +00:00
ibex_compressed_decoder.sv	[rtl] Introduce default clk/reset to prim_assert	2020-02-10 09:42:52 +00:00
ibex_controller.sv	[rtl] Introduce default clk/reset to prim_assert	2020-02-10 09:42:52 +00:00
ibex_core.f	Add local fast interrupts, remove legacy interrupts	2019-07-24 14:22:00 +01:00
ibex_core.sv	[rtl] Fix assertion issues	2020-02-10 17:01:38 +00:00
ibex_core_tracing.sv	[RTL] Added seperate ALU for branch target	2020-01-31 09:32:20 +00:00
ibex_cs_registers.sv	[rtl] Change misa for RV32E	2020-02-20 14:29:32 +00:00
ibex_decoder.sv	[rtl] Introduce default clk/reset to prim_assert	2020-02-10 09:42:52 +00:00
ibex_ex_block.sv	[rtl] Add Single Cycle Multiplier targeting FPGA	2020-02-11 16:09:41 +01:00
ibex_fetch_fifo.sv	[rtl] Introduce default clk/reset to prim_assert	2020-02-10 09:42:52 +00:00
ibex_id_stage.sv	[rtl] Fix assertion issues	2020-02-10 17:01:38 +00:00
ibex_if_stage.sv	Split have_instr definition out of always block in if_stage	2020-03-02 12:42:17 +00:00
ibex_load_store_unit.sv	[rtl] Fix assertion issues	2020-02-10 17:01:38 +00:00
ibex_multdiv_fast.sv	[rtl] Alter multdiv to better match style guide	2020-02-17 13:41:55 +00:00
ibex_multdiv_slow.sv	Reduce latency of slow multiplier	2020-02-10 18:28:14 +01:00
ibex_pkg.sv	[rtl] Decouple mip and mie CSRs	2020-02-04 16:15:38 +01:00
ibex_pmp.sv	[RTL PMP] Fix address matching bugs	2019-10-03 10:41:29 +01:00
ibex_prefetch_buffer.sv	[rtl] Implement FENCE.I	2019-11-27 08:47:26 +00:00
ibex_register_file_ff.sv	Mention CREDITS.md in license header	2019-08-27 18:10:02 +01:00
ibex_register_file_fpga.sv	[rtl] Fix Typo in FPGA Register File	2020-01-20 17:01:30 +00:00
ibex_register_file_latch.sv	Register file: update comments	2019-08-29 15:24:18 +01:00
ibex_tracer.sv	Tracer: Mark all functions "automatic"	2020-02-21 10:31:05 +00:00
ibex_tracer_pkg.sv	Implement Verilator-compatible tracer, and use it	2019-10-02 18:28:26 +01:00